CSC227: Operating

Systems Spring
2017

CHAPTER 1

MEMORY
STRUCTURE
 Memory Types
Memories Speeds
Direct Memory Access (DMA)
LAYOU

Cache Memory
T

2
 MEMORY TYPES (1)
Read-Only Memory (ROM)
Cannot be erased.
Used to store static programs such as bootstrap program & game cartridges.
Electrically Erasable Programmable ROM (EEPROM)

Can be erased, but not frequently.

Contains static programs such as those installed by the factory in smartphones.
Flash memory is a special form of EEPROM.
Registers
High-speed memory located on the processor chip (on-chip).
STRUCTURE

Holds data for immediate use by the processor.

MEMORY

They are the fastest amongst memory types.They have the same speed as the
processor.
They are the most expensive.
They have very low capacity, only a few bytes.
They are volatile.

Cache Memory
Main Memory
Hard Disk
Magnetic, Optical Disks and
Magnetic Tapes
3
 MEMORY TYPES (2)
Read-Only Memory (ROM)
Electrically Erasable Programmable ROM
(EEPROM)
Registers
Cache
Memory
Relatively
high-speed
Main
memory Memory
as
compared
Any to to be executed should be first loaded into the main memory.
program
STRUCTURE

main memory.
Also, any data to be processed should be first loaded into the main memory.
MEMORY

located close to the processor (on-chip or

Slower than the cache memory.
off-chip). Auxiliary memory, rewritable
It has high capacity, rewritable and volatile.
and volatile.
Hard Disk
A secondary storage device.
It has a low speed as compared to the main memory.
It has high capacity, rewritable and non-volatile.

Magnetic, Optical Disks and

Magnetic Tapes
A secondary storage device.
It
It has
has a lower
high speed rewritable
capacity, as compared
andto the
hard disk.
 MEMORIES SPEEDS

0 HIGHEST HIGHEST LOWEST

cycles
2 - 10 cycles

30 cycles
STRUCTURE
MEMORY

About
106
cycles
LOWEST LOWEST HIGHEST

COST PER BIT SPEED CAPACITY

Latency is measured in
processor cycles.
5
 MEMORIES MAIN CHARACTERISTICS

Semi-conductor
technology
Volatile

Secondary
STRUCTURE

Storage
MEMORY

6
 DIRECT MEMORY ACCESS (DMA) TECHNIQUE FOR I/O

DMA is used for high-speed I/O devices that are able to transmit information
at a speed close to that of the main memory.

In this technique, the device controller transfers an entire block of data (rather
than bytes)
directly to or from its own buffer storage to memory, with no intervention from
Only one interrupt is generated per block, rather than per byte, to tell the
the CPU.
device driver that the
operation is completed.
While the device controller is performing these operations, the CPU is
STRUCTURE

available to accomplish other work.

MEMORY

7
 DIRECT MEMORY ACCESS (DMA) TECHNIQUE I/O DETAILED STEPS
FOR
Main Memory

Memory Controller

I/O
Disk
Controll
er
STRUCTURE
MEMORY

CPU

Step 1:
A processor sends an I/O request to the I/O controller, which sends the
request to the disk. The processor continues executing instructions.
Step 2:
The disk sends data to the I/O controller; the data is placed at the memory
address specified by the DMA command.
Step 3:
The disk sends an interrupt to the processor to indicate that the I/O is done.
Dr. Soha S. Zaghloul
8
 CACHE MEMORY - INTRODUCTION

0
cycles

2 - 10
cycles

30
cycles
STRUCTURE
MEMORY

If the CPU needs to read/write from/into the memory, it stays idle until the
needed variables are fetched (accessed).

The cache speeds the access of the CPU to the

needed variables.
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 CACHE MEMORY HIT/MISS

Caches are used in the

following way:
Step 1:
When the CPU needs an address (data/instruction), it looks for it in the
cache.
Step 2:
If found, we say that we have a cache hit.The address contents are
returned to the CPU. The CPU uses them in its processing.Thus,
multiple cycles are saved as compared to fetching the address
contents from the main memory.
Step 3:
STRUCTURE

If not found, we say that we have a cache miss.The CPU then searches
for the address in the main memory.
MEMORY

Step 4:
In the latter case, the CPU fetches the address contents from the main
memory. A copy is
also stored in the cache for possible future reference.
Thus, the contents of a cache is always a subset of those of a main memory.

1
 CACHE MEMORY ILLUSTRATION

Addre
ss
Mai
CPU Dat CACHE
a
Memor
n
y

(1) CACHE
STRUCTURE

HIT
MEMORY

Addre Addre
ss ss
CACHE
Main
CPU Copy of Memor
Data
y
Dat
a

(2) CACHE
MISS

1
Dr. Soha S.
Zaghloul
 CACHE MEMORY PERFORMANCE

The performance of a cache memory is calculated as follows:

Number of cache hits

Performance = ----------------------------------------- *
100%
Total number of cache access
Example:
A CPU accesses the cache 1000 times.The addresses are found 500
times.What is the performance of the cache?
Solution:
STRUCTURE

500
MEMORY

Performance = ------------ * 100%

= 50% 1000

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 CACHE MEMORY MULTI-LEVEL CACHES

Multiple caches may be used. In this case, they are

used as follows:
Step 1:
The CPU searches for an address in Level-1 cache.
Step 2:
If found, the address contents are returned to the CPU.
Step 3:
If not found, the CPU searches for the address in Level-2 cache.
Step 4:
STRUCTURE

If the address is found in Level-2 cache, then the address contents

MEMORY

are returned to the processor, and a copy is made in Level-1 cache.

Step 5:
If the address is not found in Level-2 cache, then the CPU searches for it
in the main memory.Address contents are submitted to the CPU.Two
copies are made for both Level- 1 and Level-2 caches.

In such an architecture, the contents of L1-cache are subset of L2-cache.The

latter is subset of the main memory.
Note that
In such thethe
case access to L1 cache
performance is higher
of each than
cache that to L2 cache.The
is calculated separately. latter
is higher than the access time to main memory.

1
 CACHE MEMORY MULTI- CACHE ARCHITECTURE
LEVEL

Address
Data

CPU Data L1-CACHE Main

Address
Memor
y
STRUCTURE

Data Data
Addres
MEMORY

L2-CACHE s

Data Data

1
 CACHE MEMORY PERFORMANCE OF MULTI-LEVEL CACHES

The miss rate of level-1 cache:

Number of L1-cache misses

L1 Miss rate (L1miss) = ----------------------------------------- * 100%
Total number of cache access

The miss rate of level-2 cache:

Number of L2-cache misses

L2 Miss rate (L2miss) = -----------------------------------------*L1miss * 100%
STRUCTURE

Total number of cache access

MEMORY

Note that the following formula is always true:

Miss ratio = 1 Hit Ratio