L14 Physical Design

6.375 Spring 2007

Ajay Joshi

Massachusetts Institute of Technology

1
 RTL design flow

HDL

RTL manual
Synthesis design

netlist a

b
0
1
d
q

Library/ s clk

module Logic
generators optimization

a 0 d
netlist b 1
q

s clk

physical
design

layout

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Physical design overall flow
Partitioning

Floorplanning

Placement
Improvement
Cost Estimation
Routing Region
Definition

Global Routing
Improvement
Cost Estimation

Detailed Routing
Improvement
Cost Estimation

Compaction/clean-up

Write Layout Database

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 Partitioning
Decompose a large complex system into
smaller subsystems
Decompose hierarchically until each
subsystem is of manageable size
Design each subsystem separately to speed
up the process
Minimize connection between two
subsystems to reduce interdependency

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Partitioning at different levels*

* Sherwani 92
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Partitioning example*

* Sherwani 92

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 Partitioning problem
Objective:
Minimize interconnections between partitions
Minimize delay due to partitioning
Constraints
Number of terminals in each subsystem (Count (Vi) <
Ti)
Area of each partition (Aimin < Area(Vi) < Aimax)
Number of partitions (Kmin < k < Kmax)
Critical path should not cut boundaries

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 Kernighan-Lin algorithm
Input: Graph representation of the circuit
Output: Two subsets of equal sizes
Bisecting algorithm :
Initial bisection
Vertex pairs which gives the largest decrease in
cutsize are exchanged
Exchanged vertices are locked
If no improvement is possible and some vertices
are still unlocked then vertices which give smallest
increase are exchanged

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K-L algorithm example*

* Sherwani 92
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 Partitioning methods
Top-down partitioning
Iterative improvement
Spectral based
Clustering methods
Network flow based
Analytical based
Multi-level
Bottom-up clustering
Unit delay model
General delay model
Sequential circuits with retiming

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Physical design overall flow
Partitioning

Floorplanning

Placement
Improvement
Cost Estimation
Routing Region
Definition

Global Routing
Improvement
Cost Estimation

Detailed Routing
Improvement
Cost Estimation

Compaction/clean-up

Write Layout Database

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 Floorplanning
Output from partitioning used for
floorplanning
Inputs:
Blocks with well-defined shapes and area
Blocks with approximated area and no particular
shape
Netlist specifying block connections
Outputs:
Locations for all blocks

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 Floorplanning problem*
Objectives
Minimize area
Reduce wirelength
Maximize routability
Determine shapes
of flexible blocks
Constraints
Shape of each block
Area of each block
Pin locations for
each block
Aspect ratio

* Sung Kyu Lim

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 Slicing floorplan sizing*
General case: all modules are soft macros
Phase 1: bottom-up
Input floorplan tree, modules shapes
Start with a sorted shapes list of modules
Perform vertical_node_sizing and
horizontal_node_sizing
On reaching the root node, we have a list of
shapes, select the one that is best in terms of area
Phase 2: top-down
Traverse the floorplan tree and set module
locations

* Sung Kyu Lim

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Sizing example*

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* Sung Kyu
 Floorplanning Algorithms
Stockmeyer algorithm
Simulated annealing
Linear programming
Sequence-pair based floorplanning

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Floorplanning - Encounter

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Physical design overall flow
Partitioning

Floorplanning

Placement
Improvement
Cost Estimation
Routing Region
Definition

Global Routing
Improvement
Cost Estimation

Detailed Routing
Improvement
Cost Estimation

Compaction/clean-up

Write Layout Database

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 Placement
The process of arranging circuit components
on a layout surface
Inputs : Set of fixed modules, netlist
Output : Best position for each module based
on various cost functions
Cost functions include wirelength, wire
routability, hotspots, performance, I/O pads

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Good placement vs Bad placement*

Good placement Bad placement

No congestion Congestion
Shorter wires Longer wire lengths
Less metal levels
More metal levels
Smaller delay
Longer delay
Lower power dissipation
Higher power dissipation
* S. Devadas
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 Simulated annealing algorithm
Global optimization technique
Cooling schedule is adopted
An action performed at each new
temperature
Estimate the cost associated with an action
If new cost < old cost accept the action
If new cost > old cost then accept the action
with probability p
Probability p depends on a temperature
schedule Higher p at higher temperature

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Annealing curve

* Sherwani 92
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Placement using simulated annealing
Use initial placement results e.g. random
placement
Two stage process*
Stage 1
Modules moved between different rows and same row
Module overlaps allowed
Stage two begins when temperature falls below a certain
value
Stage 2
Module overlaps removed
Annealing continued, but interchange adjacent modules
in the same row

* Sechen DAC86
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 Placement methods
Constructive methods
Cluster growth algorithm
Force-directed method
Algorithm by Goto
Min-cut based algorithm
Iterative improvement methods
Pairwise exchange
Simulated annealing Timberwolf
Genetic algorithm
Analytical methods
Gordian, Gordian-L

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Placement - Encounter

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Optimized placement - Encounter

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Physical design overall flow
Partitioning

Floorplanning

Placement
Improvement
Cost Estimation
Routing Region
Definition

Global Routing
Improvement
Cost Estimation

Detailed Routing
Improvement
Cost Estimation

Compaction/clean-up

Write Layout Database

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 Routing
Connect the various standard cells using
wires
Input:
Cell locations, netlist
Output:
Geometric layout of each net connecting various
standard cells
Two-step process
Global routing
Detailed routing

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Global routing vs detailed routing*

* Sung Kyu Lim

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 Routing problem formulation
Objective
100% connectivity of a system
Minimize area
Minimize wirelength
Constraints
Number of routing layers
Design rules
Timing (delay)
Crosstalk
Process variations

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Maze routing - example

* Sung Kyu Lim

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 Maze routing
Mainly for single-layer routing
Strengths
Finds a connection between two terminals if it
exists
Weakness
Large memory required as dense layout
Slow
Application global routing, detailed routing

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 Routing algorithms
Global routing
Maze routing
Cong/Preas algorithm
Spanning tree algorithm
Steiner tree algorithm
Detailed routing
2-L Channel routing: Basic left-edge algorithm
Y-K algorithm

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Detailed routing - Encounter

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Critical path - Encounter

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Specialized routing

* Sherwani 92
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Clock distribution - Encounter

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Power routing*

*6.884 Spring 2005

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 Power distribution issues

Kaveh Shakeri
Noise in power supply
IR drop (static)
L di/dt (transient)
Electromigration
Solution: decoupling capacitance, wire
material

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 Summary
Looked at the physical design flow
Involved several steps
Partitioning
Floorplanning
Placement
Routing
Each step can be formulated as an
optimization problem
Need to go through 2 or more iterations in
each step to generate an optimized solution

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