Class: ECE 6466 “IC
Engineering”
Instructor: Dr. W.
Zagozdzon-Wosik
Text Book:
Silicon VLSI Technology
Fundamentals, Practice and
Modeling
Authors: J. D. Plummer, M. D.
Deal,
and P. B. Griffin
INTRODUCTION - Chapter 1 in the Text
• This course is basically about silicon chip fabrication, the technologies used to
manufacture ICs.
• We will place a special emphasis on computer simulation tools to help
understand these processes and as design tools.
• These simulation tools are more sophisticated in some technology areas than in
others, but in all areas they have made tremendous progress in recent years.
• 1960 and 1990 integrated circuits.
• Progress due to: Feature size reduction - 0.7X/3 years (Moore’s Law).
Increasing chip size - ≈ 16% per year.
“Creativity” in implementing functions.
Evolution of the Silicon Integrated Circuits
since 1960s
Increasing: circuit complexity, packing
density, chip size, speed, and reliability
Decreasing: feature size, price per bit,
power (delay) product
1960s
1990
s
G. Marcyk
Feature Size Device Scaling Over Time
~13% decrease in feature size each year
100µm (now: ~10%)
Era of Simple Scaling
10µm ~16% increase in complexity Cell dimensions
each year (now:6.3% for µP,
12% for DRAM)
1µm
0.25µm in 1997 Scaling + Innovation
130 nm in 2002 (ITRS)
0.1µm
Invention
10nm 18 nm in 2018
Transition Region
Atomic dimensions
1nm Quantum Effects Dominate
Atomic Dimensions
0.1nm
1960 1980 2000 2020 2040 Year
• The era of “easy” scaling is over. We are now in a period where
technology and device innovations are required. Beyond 2020, new
currently unknown inventions will be required.
1999 2001 2004 2007 201 201 201
1997
0 3 6
2 nodes
G. Marcyk, Intel
Trends in Scaling
Si Microeletronics and MEMS
Trends in Increasing Integration Scale of Circuits
Past, Present, and Future ICs
Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018
Technology Node (half pitch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm
MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm
DRAM Bits/Chip (Sampling) 256M 512M 1G 4G 16G 32G 64G 128G 128G
MPU Transistors/Chip (x106) 550 1100 2200 4400 8800 14,000
Min Supply Voltage (volts) 1.8-2.5 1.5-1.8 1.2-1.5 0.9-1.2 0.8-1.1 0.7-1-0 06-0.9 0.5-0.8 0.5-0.7
ITRS at http://public.itrs.net/ (2003 version + 2004 update) – on class website.
• Assumes CMOS technology dominates over entire roadmap.
• 2 year cycle moving to 3 years (scaling + innovation now required).
• 1990 IBM demo of Å scale “lithography”.
• Technology appears to be capable of making structures much smaller than
currently known device limits.
Historical Perspective
• Invention of the bipolar
transistor - 1947, Bell Labs.
• Shockley’s “creative failure”
methodology
N
N
P
P
N
N
• Grown junction transistor
technology of the 1950s
N P N
N
Building Blocks of Integrated Circuits
Bipolar Transistors(BJT) and Metal Oxide Semiconductor Field Effect
Transistors (MOSFET) with n- and p-type channels.
• Alloy junction technology of the 1950s.
Fabrication of Bipolar Transistors in the 1950s
Ge used as a crystal, III and V group atoms used
as dopants
3rd group
N
N
P
P
N
N
Al wires
N P N
N
p-n-p transistor
Exposed junctions had degraded surface properties and no possibility of connecting multiple
devices
Evolution of the Fabrication Process
The Mesa Design of Bipolar Transistors
Bell Lab, 1957, Double Diffused Process
Contacts
alloyed N
N P
Solid state B
diffusion
P
Mesa etched
N
Solid state P diffusion N
Advantage: Connection of
multiple devices but no ICs
Disadvantage: Degradation by
exposed junctions at the surface
Si O 2
P
N
• The planar process (Hoerni -
N
Fairchild, late 1950s).
P
N
• First “passivated” junctions.
Light
Mask
Photoresist
Deposited Film
• Basic lithography process
Substrate
which is central to today’s
Film deposition Photoresist application Exposure chip fabrication.
Etch mask
Development Etching Resist removal
Evolution of the Fabrication Process: The Planar Design of
Bipolar Transistors
Beginning of the Silicon Technology and the End of Ge devices
Implementation of a masking oxide to protect
junctions at the Si surface
Oxidation Lithogra
possible Si O 2
phy to
for Si not open
good for Ge N
P
window
in SiO2
SiO2 Boron diffusion N
Mask
Phospho
rus
N
N
diffusi
on
P
Oxidation and
outdiffusion through
P
N
the
oxide
N
mask
The planar process of Hoerni and Fairchild (1950
Beginning of Integrated Circuits in 1959
Kilby (TI) and Noyce (Fairchild Semiconductors)
Photolithography used for Pattern Formation
Light
Mask
Photoresist • Sensitive to light
Deposited Film • Durable in etching
Substrate
Film deposition Photoresist application Exposure
Etch mask
Development Etching Resist removal
• Basic lithography process
which is central to today’s
chip fabrication.
Alignment of Layers to Fabricate IC Elements
• Lithographic process allows integration of multiple devices side by side on a
wafer.
• Bipolar Transistor and resistors made in the base region
•Accuracy of placement ~1/4 to 1/3 of the linewidth being printed
BJT
B
0V
Vcc
C E
N P N P
P Resistor Base
R=L/W•Rs
Emitter Resistor
Contact to collector
N
Collector
Schematic Cross-Section of Modern CMOS Integrated Circuit with
Two Metal Levels
IC is located
at the
surface of a Interconnect
Si wafer M2
(~500µm OXIDE
thick) Via
M1
Silicide TiN
Oxide Isolation
P+ N P+ N+ P N+
PMOS NMOS
N Well P Well
P
Modern IC with a Five Level Metallization Scheme.
P
l
a
n
a
r
i
z
a
t
i
o
n
• Actual cross-section of a modern
microprocessor chip. Note the
multiple levels of metal and
planarization. (Intel website).
Computer Simulation Tools (TCAD)
•Most of the basic technologies in silicon chip manufacturing can now be simulated.
Simulation is now used for:
• Designing new processes and devices.
• Exploring the limits of semiconductor devices and technology (R&D).
• “Centering” manufacturing processes.
• Solving manufacturing problems (what-if?)
• Simulation of an
advanced local
oxidation process.
• Simulation of
photoresist exposure.
