Testing of Digital Circuits

M. Balakrishnan
Dept. of Comp. Sci. & Engg.
I.I.T. Delhi

Chapter 7: Testing Of Digital Circuits 1

 Design Approaches

• Test pattern generation to cover a large

fraction of the faults
• Design for testability
– Built-in-self-test (BIST)

• Fault tolerant design

Chapter 7: Testing Of Digital Circuits 2
 Faults: Sources and Types
• Sources
– Design process
– Device defects
– Manufacturing process
• Types
– Dynamic
– Static

Chapter 7: Testing Of Digital Circuits 3

 Fault Models
• Stuck-at faults correspond to a simple fault
model
– Stuck-at-0 (s-a-0)
– Stuck-at-1 (s-a-1)
• More complex models are also used but
beyond the scope of this work

Chapter 7: Testing Of Digital Circuits 4

 Combinational Circuits: Test
Pattern Generation
Problem definition:

Given a set of faults (F) and a set of test

vectors (T), identify the smallest possible
subset of test vectors (V) which covers
either all the faults in F or say a
predetermined fraction of faults (say 98%).

Chapter 7: Testing Of Digital Circuits 5

 Fault Simulation
Given a test vector, by simulating the circuit
with the fault, identify all faults covered by
the test vector.

Test
vectors (T) Faults (F)

Chapter 7: Testing Of Digital Circuits 6

 Test Generation
• Given a fault, identify all the test vectors
which can cover that fault.

Test
vectors (T) Faults (F)

Chapter 7: Testing Of Digital Circuits 7

 Limitations
• Only one fault is expected to occur at one time
• Faults other than stuck-at faults are expected
to show up as stuck-at faults at some other
location
• By and large fault location is not possible
• These approaches are valid only for
combinational circuits

Chapter 7: Testing Of Digital Circuits 8

 Typical Circuit Enhancements

• Insertion of test points

• Pin amplification
• Test modes
• Scan chains

Chapter 7: Testing Of Digital Circuits 9

 Test Generation Methods

M. Balakrishnan
Dept. of Comp. Sci. & Engg.
I.I.T. Delhi

Chapter 7: Testing Of Digital Circuits 10

 Parallel Fault Simulation

• In parallel fault simulation, evaluation is

performed simultaneously for many faults

• The number of faults that can be

simultaneously simulated corresponds the
word length of the host machine

Chapter 7: Testing Of Digital Circuits 11

 Parallel Fault Simulation
(Example)

a i
b f
c h

d g
e

Chapter 7: Testing Of Digital Circuits 12

 Parallel Fault Simulation
(Example contd.)
ff a0 a1 b0 b1 c0 c1 d0
a 0 0 1 0 0 0 0 0
b 1 1 1 0 1 1 1 1
c 0 0 0 0 0 0 1 0
d 1 1 1 1 1 1 1 0
e 0 0 0 0 0 0 0 0
f 0 0 0 0 0 0 1 0
g 0 0 0 0 0 0 0 1
h 1 1 1 1 1 1 1 1
i 1 1 1 1 1 1 1 1

Chapter 7: Testing Of Digital Circuits 13

 Deductive Fault Simulation
• At each of the primary inputs generate the
list of faults that can be detected by the test
vector
• Use these lists to generate the lists at other
nodes by “appropriate” operations on these
lists

Chapter 7: Testing Of Digital Circuits 14

 Deductive Fault Simulation
(example)
La = {a1} Lb = {b0} Lc = {c1} Ld = {d0} Le = {e1}
a 0 1 i
b 1 f
c 0 h Lfp = Lb’  Lc = {c1}
0 Lf = {c1, f1}
1 Lgp = (Ld’  Le)’ = {d0}
d 1 0g Lg = {d0, g1}
0 Lhp’ = (Lf  Lg)’, Lhp = 
e
Lh = {h0}
Lip’ = La  Lh’, Lip = {h0}
Li = {h0, i0}
Chapter 7: Testing Of Digital Circuits 15
 Deductive Fault Simulation
(example contd.)
La = {a1} Lb = {b0} Lc = {c0} Ld = {d0} Le = {e1}
a 0 1 i
b 1 f
c 1 h Lfp’ = Lb’  Lc’ = { b0, c0}
1 Lf = {b0, c0, f0}
1 Lgp = (Ld’  Le)’ = {d0}
d 1 0g Lg = {d0, g1}
0 Lhp’ = (Lf ‘ Lg)’
e
Lhp = {d0,g1} , Lh = {d0,g1,h0}
Lip’ = La  Lh’, Lip = {d0, g1,h0}
Li = {d0, g1, h0, i0}
Chapter 7: Testing Of Digital Circuits 16
 Test Generation Methods
Boolean Difference & D-Algorithm
M. Balakrishnan
Dept. of Comp. Sci. & Engg.
I.I.T. Delhi

Chapter 7: Testing Of Digital Circuits 17

 Boolean Difference
Consider a function f of say 4 variables
f(x0, x1, x2, x3)
Boolean difference of f w.r.t to xi is defined as
follows:
df/dxi = fxi=0 + fxi=1

Chapter 7: Testing Of Digital Circuits 18

 Boolean Difference (example)
a i
b f
c h

d g
e i = a + ((b.c). (d +e)’)’
di/da = ia=0 + ia=1
= ((b.c).(d+e)’)’ + 1 = (b.c)(d+e)’
Chapter 7: Testing Of Digital Circuits 19
 Example (contd.)
di/da = (b.c)(d+e)’
s-a-0 fault at a can be tested by
a.di/da = 1 or a.b.c(d+e)’ = 1
 test vectors (1,1,1,0,0)
s-a-1 fault at a can be tested by
a’.di/da = 1 or a’.b.c(d+e)’ = 1
 test vectors (0,1,1,0,0)
Chapter 7: Testing Of Digital Circuits 20
 Boolean Difference (contd.)
a
b f
c h

d g
e i = a + (f. (d +e)’)’
di/df = if=0 + if=1 = 1 + (a +d+e)
= (a+d+e)’ = a’d’e’
Chapter 7: Testing Of Digital Circuits 21
 Boolean Difference (contd.)
di/df = a’.d’.e’
s-a-0 fault at f can be tested by
f.di/df = 1 or fa’d’e’ = b.c.a’d’e’ =1
 test vectors (0,1,1,0,0)
s-a-01fault at f can be tested by
f’.di/df = 1 or f’.a’d’e’ = (b.c)’.a’d’e’ = 1
 test vectors (0,0,X,0,0) and (0, X,0,0,0)
Chapter 7: Testing Of Digital Circuits 22
 D-Algorithm
There are three main steps in the D-Algorithm
• Generate the fault
• Propagate the fault to one of the outputs
(Forward or D-Drive)
• Back propagate to get consistent assignment
for inputs (Backward drive or back-
propagation)
Chapter 7: Testing Of Digital Circuits 23
 D-Algorithm (Step 1)
a i
4
b f
c 1
h
3
d g Let us say we choose
e 2
the fault g node s-a-0
Assign inputs to gate 2 to generate the fault
i.e. d = 0 and e = 0
Chapter 7: Testing Of Digital Circuits 24
 D-Algorithm (Step 2)
a i
4
b f
c 1
h
3
d 0 D g
0 2
Choose a path to the o/p
e
and propagate the fault
f is to be assigned 1 and a is to be assigned 0
to propagate D to the output i
Chapter 7: Testing Of Digital Circuits 25
 D-Algorithm (Step 3)
a 0
D’ i
4
b f
c 1
1 h D’
3
d 0 D g
0 2
Consistency Check
e

Assign inputs to gates (whose outputs have been

specified ) consistent with other assignments
Chapter 7: Testing Of Digital Circuits 26
 D-Algorithm Result
a 0
D’ i
4
b 1 f
c 1
1 1 h D’
3
d 0 D g
e 0 2

The test vector is (0,1,1,0,0)

Chapter 7: Testing Of Digital Circuits 27

 D-Algorithm

M. Balakrishnan
Dept. of Comp. Sci. & Engg.
I.I.T. Delhi

Chapter 7: Testing Of Digital Circuits 28

 Terminology

• Singular Cover
• D-intersection
• Primitive D-cube of a fault (pdcf)
• Propagation D-cubes (pdf)

Chapter 7: Testing Of Digital Circuits 29

 Singular Cover
SC of a gate (or any circuit element) is
nothing but a compact version of the truth
table. SC of a AND gate with a and b as
inputs and c as output
a b c
0 X 0
X 0 0
1 1 1
Chapter 7: Testing Of Digital Circuits 30
 Singular Cover (contd.)
SC of a NOR gate with a and b as inputs and c
as output
a b c
1 X 0
X 1 0
0 0 1

Chapter 7: Testing Of Digital Circuits 31

 D-Intersection

0 1 X D D'
0 0 D' 0  
1 D 1 1  
X 0 1 X D D'
D   D D *
D'   D' * D'

Chapter 7: Testing Of Digital Circuits 32

Primitive D-Cube of Fault (pdcf)
For generating a s-a-0 fault at node c,
choose a SC row which gives an o/p of 1
for the nor gate and intersect with (X,X,0).
pdcf is (0, 0, D)

a c
b

Chapter 7: Testing Of Digital Circuits 33

 PDCF (contd.)
For generating a s-a-1 fault at node c,
choose a SC row which gives an o/p of 0
for the nor gate and intersect with (X,X,1).
pdcf is (1, X, D) or (X, 1, D)

a c
b

Chapter 7: Testing Of Digital Circuits 34

 Propagation D-Cube (pdc)
• PDC consists of a table for each circuit
element which has entries for propagating
faults on any one of its inputs to the output.
• To generate PDC entry corresponding to any
one column, D-intersect any two rows of SC
which have opposite values (0 and 1) in that
column.
• There can be multiple rows for one column
Chapter 7: Testing Of Digital Circuits 35
 PDC Example
PDC of a AND gate with a and b as inputs
and c as output

a b c
1 D D
D 1 D

Chapter 7: Testing Of Digital Circuits 36

 PDC Example (contd.)
PDC of a NOR gate with a and b as inputs
and c as output

a b c
0 D D’
D 0 D’

Chapter 7: Testing Of Digital Circuits 37

 D-Algorithm Steps
• Choose a stuck-at-fault at any of the nodes.
• Choose a pdcf for generating the fault.
• Choose an output and a path to the output and
propagate the fault to the output by choosing pdc
for all circuit elements on the path. (D-Drive)
• Use the SC of all unassigned circuit elements to
arrive at a consistent set of inputs. (back-propagate
or consistency check)

Chapter 7: Testing Of Digital Circuits 38

 D-Algorithm: PDCF Example
a i
4
b f
c 1
h
3
d g
e 2

Choose a fault say g s-a-0. Choose pdcf of

gate 2 for generating this fault
(a b c d e f g h i ) = (X X X 0 0 X D X X)
Chapter 7: Testing Of Digital Circuits 39
 D-Algorithm: D-Drive Example
Propagate the fault to the o/p using pdc of gates 3
&4 a i
4
b f
c 1
h
3
0 Dg
d
0 2 pdc 3 (X X X 0 0 1 D D’ X)
e
pdc 4 (0 X X 0 0 1 D D’ D’)

Chapter 7: Testing Of Digital Circuits 40

 D-Algorithm: Consistency
Example
Perform consistency operation for gate 1
a i
4
b f
c 1
h
3
0 Dg
d
0 2 (X X X 0 0 1 D D’ X)
e
sc 1 (0 1 1 0 0 1 D D’ D’)

Chapter 7: Testing Of Digital Circuits 41

 D-Algorithm: Summary
a b c d e f g h i
Initial x x x x x x x x x
pdcf 2 x x x 0 0 x D x x
pdc 3 x x x 0 0 1 D D' x
pdc 4 0 x x 0 0 1 D D' D'
consis. 1 0 1 1 0 0 1 D D' D'
D

Chapter 7: Testing Of Digital Circuits 42

 Testing of Sequential Circuits

M. Balakrishnan
Dept. of Comp. Sci. & Engg.
I.I.T. Delhi

Chapter 7: Testing Of Digital Circuits 43

 Testing Techniques

• State table verification

• Random testing
• Transition count testing
• Scan based testing
• Signature analysis

Chapter 7: Testing Of Digital Circuits 44

 State Table Verification
Verify each transition by first taking the
machine to a specific initial state, applying
the input to perform the transition and then
verifying the final state.

For this purpose we need a homing

sequence and distinguishing sequence

Chapter 7: Testing Of Digital Circuits 45

 Homing & Distinguishing
Sequence
• Homing sequence: An input is said to be a
homing sequence for a m/c if the m/c’s
response to the sequence is always sufficient
to determine uniquely its final state.
• Distinguishing sequence: An input sequence
which when applied to a machine will
produce a different output sequence for each
choice of initial state.
Chapter 7: Testing Of Digital Circuits 46
 Example
PS X=0 X=1
A B, 0 D, 0
B A, 0 B, 0
C D, 1 A, 0
D D, 1 C, 0

Chapter 7: Testing Of Digital Circuits 47

 Example: Homing Sequence
(ABCD)
0 1

(AB)(D) (ABCD)
0 1
(AB)(D) (BD)(C)
0 1
(A)(D)(D) (BC)(A)

Chapter 7: Testing Of Digital Circuits 48

 Random Testing

Circuit
Random under test
pattern Compare
generator
Known
good ckt

Chapter 7: Testing Of Digital Circuits 49

 Transition Count Testing
• Count the number of transitions for a
specific input pattern and compare with the
value stored for “good” circuits
• Reduction in data storage for storing correct
responses
• “Aliasing” errors

Chapter 7: Testing Of Digital Circuits 50

 Scan Based Testing
• Form a scan chain for all the storage
elements (“flip-flops”) in the circuit
• Use this scan chain for inserting the test
patterns as well as reading the results
• Use combinational circuit test pattern
generator methods generating test inputs

Chapter 7: Testing Of Digital Circuits 51

 Scan Based Testing (contd.)

R R R
e e logic e
logic
g g g

Chapter 7: Testing Of Digital Circuits 52

 Signature Analysis & Built-in-
self-test (BIST)
M. Balakrishnan
Dept. of Comp. Sci. & Engg.
I.I.T. Delhi

Chapter 7: Testing Of Digital Circuits 53

 Signature Analysis

• Test results available in a very compact

form and thus very suitable for BIST
• In-speed testing possible
• PRBS generators use for test pattern
generation as well as test result generation

Chapter 7: Testing Of Digital Circuits 54

 PRBS Generator
A PRBS or pseudo random binary sequence
generator consists of a long shift register
with serial input generated by taking
exclusive-or of some of the intermediate
inputs

Chapter 7: Testing Of Digital Circuits 55

 BIST Example

R R R
1 2 logic 3
logic
L2
L1

Chapter 7: Testing Of Digital Circuits 56

 BIST Registers Modes

• Normal mode (PIPO)

• PRBS generator mode
• Signature capture mode
• Scan mode

Chapter 7: Testing Of Digital Circuits 57

 BIST Steps: Example
• R1 : PRBS mode, R2: Signature mode
Generate finite number of test patterns
• R1, R2, R3: Scan mode
Scan out the signature of L1 and compare
• R2 : PRBS mode, R3: Signature mode
Generate finite number of test patterns
• R1, R2, R3: Scan mode
Scan out the signature of L2 and compare
Chapter 7: Testing Of Digital Circuits 58