THE 8086 PIN
CONFIGURATION
The 8086 Fact file
• Made by INTEL in 1978
for various applications
including P.Cs, washing
machines, intercoms
and garage door
openers.
The 8086 Fact file cont..
• It’s a 40 pin Dual-Inline package(CERDIP).
• It’s interfaced with other processors i.e
8087 and 8089 thus the minimum and
maximum mode operations.
• It has a 16-bit processor, 16-bit data bus
and a 20-bit address bus.
The 8086 Pin Configuration
Address/ Data bus
• Pins 2-16 and 39 are time multiplexed
buses used to access memory or I/O.
• They are multi-directional. i.e used for
input and output operations.
• AD0-AD7 carries low order byte data while
AD8-AD15 carries higher order byte data.
• During first clock cycle i.e T1, these buses
carry 16-bit addresses.
• During the remaining cycles,T2,T3, Tw and
T4, it carries 16-bit data.
Address/ Data bus contd.
• The address / data operation is enabled
by the ALE (Address Latch Enable)pin
number 25.
• When ALE is high (1) the bus contains an
address of memory or I/O, hence
functions as an address bus. (A0-A15)
• When ALE is low(0) the bus carries data
to or from Memory or I/O. (D0-D15)
The 8086 timing diagram ALE signal.
Address/ Status Bus
• The address / status lines are in pin 35-
38. they are time multiplexed.
• They are unidirectional.
• During the first clock cycle, (T1), they
carry the higher order 4-bit address of
the 20-bit address. (A19-A16)
• During the other cycles, they carry the
status bits. (S6-S3)
Address/ Status Bus contd.
• The multiplexed status S3-S6 indicate
the type of operation to be performed in
that cycle.
• S6 is always set to zero. i.e low.
• S5 gives the current setting of the
interrupt flag (IF).
Address/ Status Bus contd.
• S3 and S4 indicate the segment register
being used as shown in the table.
B̅H̅E̅ /S7
• BHE is multiplexed with S7.
• BHE (Bus High Enable) indicates whether
transfer of a byte is to be done on
higher-order bus i.e. AD15-AD8
• The signal is low during the first clock
cycle for read, write and Interrupt
acknowledge cycles
• During the other clock cycles, it is active,
indicating that transfer is to be made on
lower order byte.
B̅H̅E̅ /S7 contd.
• The S7 status information is always held at logic 1
throughout.
• BHE works as shown below.
MN/M̅X̅
• At pin number 33, the input pin
indicates whether the processor is to
operate at Minimum or Maximum
mode.
• The minimum mode (One
Microprocessor) is selected by applying
logic 1 to the MN/MX input pin.
• The maximum mode (Multi
microprocessor)is selected by applying
logic 0 to the MN/MX input pin.
R̅D̅
• At pin number 32, RD indicates that the
processor is performing memory or I/O
read cycle, depending on the state of
the S2 pin.
• It is low whenever the 8086 is reading
data from memory or I/O.
• This signal floats to 3-state OFF in ‘‘hold
acknowledge’’.
R̅Q̅/G̅ T̅0̅ & R̅Q̅/G̅ T̅1̅
• At pin number 31 and 30, these are the
Request/Grant signals used by the other
processors requesting the processor to release
the system bus for use. When the signal is
received by processor, then it sends
acknowledgment.
• Important to note is that RQ/GT0 has higher
priority than RQ/GT1
• In minimum mode, the HOLD indicates to the
processor that external devices are requesting
to access the address/data buses.
• HLDA signal acknowledges the HOLD signal.
LO
̅ ̅ CK̅ ̅
• At pin number 29 the signal indicates
that an instruction with a lock prefix is
being executed and the bus is NOT to be
used by another processor.
• When this signal is active, it indicates to
the other processors not to ask the CPU
to leave the system bus.
• In minimum mode, the WR ͞ (Write
Output) is low whenever the 8086 is
writing data into memory or I/O devices
depending on the status of M/IO signal.
S̅0,̅ S̅1̅ & S̅2̅
• At pins 26,27 and 28, are the status
signals that provide the status of
operation, which is used by the Bus
Controller 8288 to generate memory &
I/O control signals.
• They indicate the type of transfer to take
place during the current bus cycle.
S̅0,̅ S̅1̅ & S̅2̅ contd.
−
• The truth table is as shown. S2 S1 S0 Status
0 0 0 Interrupt
acknowledge
ment
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory
write
1 1 1 Passive
S̅0,̅ S̅1̅ & S̅2̅ contd.
• In minimum mode, pin 28 operates the
M/I ̅O̅ (output) which is signal is used to
distinguish between memory and I/O
operations.
• When it is LOW, it indicates I/O data
transfer and when it is HIGH indicates
the memory data transfer.
S̅0,̅ S̅1̅ & S̅2̅ contd.
• In minimum mode, pin 27 operates the
DT/R̅ (Data Transmit/Receive) which is
used to control data flow direction.
• High on this pin indicates that the 8086
is transmitting data and low indicated
that it is receiving the data.
S̅0,̅ S̅1̅ & S̅2̅ contd.
• In minimum mode, pin 26 operates the
DEN͞ (Data Enable) which is used to
enable Transreceiver 8286. The
transreceiver is a device used to
separate data from the address/data
bus.
• This signal informs the transceivers that
the processor is ready to send or receive
data.
QS0 & QS1
• At pin number 25 and 24, these two
output signals reflect the status of the
instruction queue.
• This status indicates the activity in the
queue during the previous clock cycle.
QS0 & QS1 contd.
The QS0 & QS1 table indicating various
states.
QS0 QS1 Status
0 0 No operation
0 1 First byte of
opcode from the
queue
1 0 Empty the queue
1 1 Subsequent byte
from the queue
QS0 & QS1 contd.
• In minimum mode, pin 25, ALE (Address
Latch Enable) indicates the availability of
a valid address on the address/data
lines.
• Pin 24 is INTA (Interrupt Acknowledge).
When the microprocessor receives this
signal, it acknowledges the interrupt.
TEST
• In pin 23, TEST, the execution of a WAIT
instruction causes the 8086 to check the logic
level at the TEST input.
• If the logic 1 is found, the microprocessor
suspend operation and goes into the idle state.
The 8086 no longer executes instructions,
instead it repeatedly checks the logic level of
the TEST input waiting for its transition back to
logic 0.
• As TEST switches to 0, execution resume with
the next instruction in the program.
• This feature can be used to synchronize the
operation of the 8086 to an event in external
hardware
READY
• At pin 22, if this signal is low, the 8086
enters into wait state. This signal is used
to synchronise slower peripherals with
the microprocessor.
• When it is high, it indicates that the
device is ready to transfer data.
• Hence it is an active high signal.
RESET
• At pin 21, the RESET is used to restart the
execution. It causes the microprocessor to
immediately terminate its present activity.
• It clears PSW, IP, DS, SS, ES and the
Instruction Queue. It then sets CS to FFFFH.
• This signal must be high for atleast 4 clock
cycles.
• When reset is removed, 8086 fetches its
next instruction from physical memory
FFFF0H.
Power Supply, Vcc and GND
• 8086 uses 5V DC ±10% supply at VCC pin
40.
• Ground is connected to pins 1 and 20.
Clock signal, CLK
• It uses pin No 19.
• Provides the basic timing square wave signal of 33% duty cycle, I.e
High for 1/3 and low for 2/3s from an external, crystal controlled
generator to synchronize internal operations.
• Operating frequency is 5MHz,(8086) 8MHz (8086-2) and 10 MHz
(8086-1) for the various 8086 variants.
INTR
• It uses pin No 18.
• It is a level-triggered, maskable interrupt request signal.
• It is sampled during the last clock cycle of each instruction to
determine if the processor should enter into an interrupt service
routine.
NMI
• It uses pin No 17.
• It stands for non-maskable interrupt.
• It is positive edge triggered input, which causes an interrupt request
to the microprocessor.
