VLSI Testing

Lecture 6: Sequential ATPG

 Problem of sequential circuit ATPG
 Time-frame expansion
 Nine-valued logic
 ATPG implementation and drivability
 Complexity of ATPG
 Cycle-free and cyclic circuits
 Asynchronous circuits
 Summary

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 1

 Sequential Circuits
 A sequential circuit has memory in addition to
combinational logic.
 Test for a fault in a sequential circuit is a
sequence of vectors, which
 Initializes the circuit to a known state
 Activates the fault, and
 Propagates the fault effect to a primary output
 Methods of sequential circuit ATPG
 Time-frame expansion methods
 Simulation-based methods

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 2

 Example: A Serial Adder
An Bn
1 1
s-a-0
D
1

1 D
X
Cn
Cn+1
X
Combinational logic 1
Sn X
FF

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 3

 Time-Frame Expansion
An-1 Bn-1 A n Bn
Time-frame -1 Time-frame 0
1 1 1
s-a-0 1
D X s-a-0
D D
1 1
Cn-1 1 D X D
Cn 1 1
Cn+1
X
1
Combinational logic Combinational logic 1
Sn-1 Sn
X
D

FF

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 4

 Concept of Time-Frames
 If the test sequence for a single stuck-at fault
contains n vectors,
 Replicate combinational logic block n times
 Place fault in each block
 Generate a test for the multiple stuck-at fault using
combinational ATPG with 9-valued logic
Vector -n+1 Vector -1 Vector 0
Fault

Unknown
Time- State Time- Time- Next
or given
frame variables frame frame state
Init. state
-n+1 -1 0
Comb.
block PO -n+1 PO -1 PO 0
Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 5
Example for Logic Systems

FF1
B

A FF2
s-a-1

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 6

 Five-Valued Logic (Roth)
0,1, D, D, X
A 0 A 0
s-a-1 s-a-1
D D
X X X
FF1 FF1

X D D
FF2 FF2

B X B X
Time-frame -1 Time-frame 0

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 7

 Nine-Valued Logic (Muth)
0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X
A 0 A X
s-a-1 s-a-1
0/1 X/1
X 0/X 0/X
FF1 FF1

X 0/1 X/1
FF2 FF2

B X B 0/1
Time-frame -1 Time-frame 0

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 8

 Implementation of ATPG
 Select a PO for fault detection based on drivability analysis.
 Place a logic value, 1/0 or 0/1, depending on fault type and
number of inversions.
 Justify the output value from PIs, considering all necessary
paths and adding backward time-frames.
 If justification is impossible, then use drivability to select
another PO and repeat justification.
 If the procedure fails for all reachable POs, then the fault is
untestable.
 If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can
be justified, the the fault is potentially detectable.

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 9

 Drivability Example
(11, 16)
(10, 15) (22, 17)
(10, 16)
d(0/1) =

8
d(0/1) = 4 s-a-1 d(1/0) = 32
d(0/1) =

8
d(1/0) =
8

d(1/0) = 20
(5, 9)
(4, 4)
(17, 11)
d(0/1) = 9
(CC0, CC1) (6, 10) d(0/1) = 120
d(1/0) = FF
8

= (6, 4) d(1/0) = 27
d(0/1) = 109
d(1/0) =

8
CC0 and CC1 are SCOAP combinational controllabilities

d(0/1) and d(1/0) of a line are effort measures for driving

a specific fault effect to that line

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 10

 Complexity of ATPG
 Synchronous circuit -- All flip-flops controlled by clocks; PI and
PO synchronized with clock:
 Cycle-free circuit – No feedback among flip-flops: Test
generation for a fault needs no more than dseq + 1 time-
frames, where dseq is the sequential depth.
 Cyclic circuit – Contains feedback among flip-flops: May
need 9Nff time-frames, where Nff is the number of flip-
flops.
 Asynchronous circuit – Higher complexity!

Smax Time- Time- S3 Time- S2 Time- S1 Time- S0

Frame Frame Frame Frame Frame
max-1 max-2 -2 -1 0

max = Number of distinct vectors with 9-valued elements = 9Nff

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 11

 Cycle-Free Circuits

 Characterized by absence of cycles among flip-

flops and a sequential depth, dseq.
 dseq is the maximum number of flip-flops on any
path between PI and PO.
 Both good and faulty circuits are initializable.
 Test sequence length for a fault is bounded by
dseq + 1.

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 12

 Cycle-Free Example
Circuit

F2

2
All faults are
F3 testable in
F1
this circuit.
3
Level = 1 F2

2
s - graph
F1 F3 dseq = 3
Level = 1 3

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 13

 Cyclic Circuit Example
Modulo-3 counter

Z
CNT F2
F1

s - graph

F1 F2

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 14

 Modulo-3 Counter
 Cyclic structure – Sequential depth is undefined.
 Circuit is not initializable. No tests can be
generated for any stuck-at fault.
 After expanding the circuit to 9Nff = 81, or fewer,
time-frames ATPG program calls any given target
fault untestable.
 Circuit can only be functionally tested by multiple
observations.
 Functional tests, when simulated, give no fault
coverage.

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 15

Adding Initializing Hardware
Initializable modulo-3 counter

Z
CNT F2
F1
s-a-0

s-a-1
CLR
s-a-1 s-a-1 Untestable fault
Potentially detectable fault

s - graph
F1 F2

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 16

 Benchmark Circuits
Circuit s1196 s1238 s1488 s1494
PI 14 14 8 8
PO 14 14 19 19
FF 18 18 6 6
Gates 529 508 653 647
Structure Cycle-free Cycle-free Cyclic Cyclic
Seq. depth 4 4 -- --
Total faults 1242 1355 1486 1506
Detected faults 1239 1283 1384 1379
Potentially detected faults 0 0 2 2
Untestable faults 3 72 26 30
Abandoned faults 0 0 76 97
Fault coverage (%) 99.8 94.7 93.1 91.6
Fault efficiency (%) 100.0 100.0 94.8 93.4
Max. sequence length 3 3 24 28
Total test vectors 313 308 525 559
Gentest CPU s (Sparc 2) 10 15 19941 19183

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 17

 Summary
 Combinational ATPG algorithms are extended:
 Time-frame expansion unrolls time as combinational array
 Nine-valued logic system
 Justification via backward time
 Cycle-free circuits:
 Require at most dseq + 1 time-frames
 Always initializable
 Cyclic circuits:
 May need 9Nff time-frames
 Circuit must be initializable
 Partial scan can make circuit cycle-free
 Asynchronous circuits: Not discussed
 See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic
Testing for Digital, Memory and Mixed-Signal VLSI Circuits,
Springer, 2000, Chapter 8.

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 18

 Problems to Solve
1. Which type of circuit is easier to test? Circle one in each:
 Combinational or sequential
 Cyclic or cycle-free
 Synchronous or asynchronous

2. What is the maximum number of input vectors that may be

needed to initialize a cycle-free circuit with k flip-flops?

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 19

 Solution
1. Which type of circuit is easier to test? Circle one in each:
 Combinational or sequential
 Cyclic or cycle-free
 Synchronous or asynchronous

2. What is the maximum number of input vectors that may

be needed to initialize a cycle-free circuit with k flip-flops?

k vectors. Because that is the maximum sequential

depth possible. An example is a k bit shift register.

Copyright 2001, Agrawal & Bushnell Lecture 6: Sequential ATPG 20