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Design and Implementation of VLSI Systems (EN1600) : Lecture 30: Array Subsystems (DRAM/ROM)

This document summarizes a lecture on array subsystems for DRAM, ROM, and non-volatile read/write memory cells. It discusses the core cells for DRAM including 1T and 3T cells, how DRAM is manufactured using trench capacitors, and DRAM subarray architectures. It also covers ROM cells including NOR and NAND implementations and how non-volatile memories use a floating transistor gate to allow programmable threshold voltages similar to flash memory. Basic erase, write, and read operations are outlined for NOR flash memories.

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ALEX SAGAR
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363 views16 pages

Design and Implementation of VLSI Systems (EN1600) : Lecture 30: Array Subsystems (DRAM/ROM)

This document summarizes a lecture on array subsystems for DRAM, ROM, and non-volatile read/write memory cells. It discusses the core cells for DRAM including 1T and 3T cells, how DRAM is manufactured using trench capacitors, and DRAM subarray architectures. It also covers ROM cells including NOR and NAND implementations and how non-volatile memories use a floating transistor gate to allow programmable threshold voltages similar to flash memory. Basic erase, write, and read operations are outlined for NOR flash memories.

Uploaded by

ALEX SAGAR
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Design and Implementation of VLSI Systems

(EN1600)
Lecture 30: Array Subsystems (DRAM/ROM)

Prof. Sherief Reda


Division of Engineering, Brown University
Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN1600 SP’08


Lecture outline

• Last time
– Memory periphery (row/column circuitry)
– Core cell: SRAM cells
• This time (different core cells)
– DRAM cells
– ROM cells
– Non Volatile Read Write (NVRW) cells

S. Reda EN1600 SP’08


3T DRAM cell
WWL
WWL write
RWL
Vdd
M3 BL1

M1 X
M2 X Vdd-Vt
Cs
RWL read

BL2 Vdd-Vt V
BL1 BL2

 No constraints on device sizes (ratioless)


 Reads are non-destructive
 Value stored at node X when writing a “1” is VWWL - Vtn

S. Reda EN1600 SP’08


1T DRAM Cell

WL write read
WL
“1” “1”

M1 X X Vdd-Vt

Cs
CBL
BL Vdd
Vdd/2 sensing

BL

Write: Cs is charged (or discharged) by asserting WL and BL


Read: Charge redistribution occurs between CBL and Cs

Read is destructive, so must refresh after read


Leakage cause stored values to “disappear” → refresh
periodically

S. Reda EN1600 SP’08


The bit line is precharged to VDD/2

S. Reda EN1600 SP’08


How DRAM cells are manufactured?

Trench
capacitor

S. Reda EN1600 SP’08


DRAM subarray architectures

rejects common mode noise

sensitive to noise
S. Reda EN1600 SP’08
ROMs

• Read-Only Memories are nonvolatile


– Retain their contents when power is removed
• Mask-programmed ROMs use one transistor per bit
– Presence or absence determines 1 or 0

S. Reda EN1600 SP’08


NOR ROMs
• 4-word x 6-bit ROM Word 0: 010101
– Represented with dot diagram
Word 1: 011001
– Dots indicate 1’s in ROM
Word 2: 100101
weak
A1 A0 pseudo-nMOS Word 3: 101010
pullups

2:4
DEC

ROM Array

Y5 Y4 Y3 Y2 Y1 Y0

Dot diagram
Looks like 6 4-input pseudo-nMOS NORs

S. Reda EN1600 SP’08


NAND ROM
V DD
Pull-up devices

BL [0] BL [1] BL [2] BL [3]

WL [0]

WL [1]

WL [2]

WL [3]

• All word lines high by default with exception of selected row


• No transistor with the selected word -> bitline pulled down
• Transistor with the selected word -> bitline remain high

S. Reda EN1600 SP’08


Non Volatile Read/Write (NVRW) memories
• Same architecture as ROM structures
• A floating transistor gate is used
• similar to traditional MOS, except that an extra polysilicon strip
is inserted between the gate and channel
• allow the threshold voltage to be progammable

Floating gate Gate


D
Source Drain

tox G

tox
S
n+ p n+_
Substrate

Device cross-section Schematic symbol

S. Reda EN1600 SP’08


Floating gate transistor programming

20 V 0V 5V

10 V 5V 20 V -5V 0V 5V
- 2.5 V

S D S D S D

Avalanche injection Removing programming Programming results in


voltage leaves charge trapped higher V T .

Process is self-timing Floating gate is surrounded


- Effectively increases by an insulator material 
Threshold voltage traps the electrons

S. Reda EN1600 SP’08


Flash Electrically Erasable ROMs

Control gate
Floating gate

erasure Thin tunneling oxide

n 1 source n 1 drain
programming
p-substrate

To erase: ground the gate and apply a 12V at the source

S. Reda EN1600 SP’08


Basic Operations in a NOR Flash Memory―
Erase

S. Reda EN1600 SP’08


Basic Operations in a NOR Flash Memory―
Write

S. Reda EN1600 SP’08


Basic Operations in a NOR Flash Memory―
Read

S. Reda EN1600 SP’08

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