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I2C (Inter Integrated Circuit)

I2C is a half-duplex, multi-master, multi-slave serial communication protocol that uses only two bidirectional open-drain lines: serial clock (SCL) and serial data (SDA). It allows up to 128 devices on the same bus and supports standard speeds up to 100kHz and fast mode up to 400kHz. Data is transferred between a master and slave in sequences of 8-bit bytes, with an acknowledge bit sent after each byte. Device addressing uses 7-bit or extended 10-bit addresses, with the read/write bit distinguishing read from write operations.

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0% found this document useful (0 votes)
29 views

I2C (Inter Integrated Circuit)

I2C is a half-duplex, multi-master, multi-slave serial communication protocol that uses only two bidirectional open-drain lines: serial clock (SCL) and serial data (SDA). It allows up to 128 devices on the same bus and supports standard speeds up to 100kHz and fast mode up to 400kHz. Data is transferred between a master and slave in sequences of 8-bit bytes, with an acknowledge bit sent after each byte. Device addressing uses 7-bit or extended 10-bit addresses, with the read/write bit distinguishing read from write operations.

Uploaded by

aravind
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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I2C

(INTER INTEGRATED
CIRCUIT)
 I2C is a Protocol
 Serial synchronous Communication
 Half Duplex Communication
 Multi Master Multi Slave Communication
Structure of I2C

 It has only two lines


 SCL(Clock Line)
 SDA(Data Line)
 SCL and SDA lines are "open drain" drivers
Start and Stop conditions

 Start:
 while SCL high: make SDA high to low
 Stop:
 while SCL high: make SDA low to high
Data Transfer

 Data is transferred in sequences of 8 bits


 The bits are placed on the SDA line starting with the MSB (Most
Significant Bit)
 The SCL line is then pulsed high, then low
 For every 8 bits transferred, the device receiving the data sends
back an acknowledge bit
Data Transfer

 so there are actually 9 SCL clock pulses to transfer each 8 bit byte
of data
 If the receiving device sends back a low ACK bit, then it has
received the data and is ready to accept another byte.
 If it sends back a high then it is indicating it cannot accept any
further data and the master should terminate the transfer by
sending a stop sequence
How fast is I2C?

 The standard clock (SCL) speed for I2C up to 100KHz


 Fast mode, which is up to 400KHz
 High Speed mode which is up to 3.4MHz
I2C Device Addressing

 All I2C addresses are either 7 bits or 10 bits


 Standard I2C: 7 bits
 Extended I2C:10 bits
 Standard I2C can have up to 128 devices on the I2C bus, since a
7bit number can be from 0 to 127.
I2C Device Addressing

 When sending out the 7 bit address, we still always send 8 bits
 The extra bit is used to inform the slave if the master is writing to
it or reading from it.
 If the bit is zero the master is writing to the slave. If the bit is 1
the master is reading from the slave.
 The 7 bit address is placed in the upper 7 bits of the byte and the
Read/Write (R/W) bit is in the LSB (Least Significant Bit).
Master to Slave Data Transfer

 Send a start sequence


 Send the I2C address of the slave with the R/W bit low (even
address)
 Send the internal register number you want to write to
 Send the data byte
 Optionally, send any further data bytes
 Send the stop sequence.
Slave to master Data Receive

 Send a start sequence


 I2C address of the Slave with the R/W bit low (even address)
 Send Internal address of the bearing register
 Send a start sequence again (repeated start)
 I2C address of the Slave with the R/W bit high (odd address)
 Read data byte from Slave
 Send the stop sequence.
Transfer and Receive
Thank you

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