Advanced topics - FPGA Synthesis, PnR, STA
BY
KALAIVANI
Typical Flow
Available Synthesis Tools
Xilinx Synthesis Tool (XST):
Advantages: Bundled with Xilinx ISE, Can automatically infer Xilinx
FPGA components, runs on UNIX (Solaris and GNU/Linux)
Disadvantaegs: Still buggy, Only supports Xilinx devices
Vendor: Xilinx
Status: Active support from Xilinx
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Available Synthesis Tools (contd...)
Leonardo Spectrum:
Advantages: Supports large family of FPGA devices, Reliable, Can
automatically infer FPGA components
Disadvantages: Runs on Solaris, Replaced by Precision-RTL
Vendor: Mentor Graphics
Status: To be replaced soon
Synplify:
Advantages: Most trusted in industry, Support large family of FPGA
devices, Can automatically infer FPGA components
Disadvantages: Some optimizers are still buggy (FPGA Compiler)
Vendor: Synplicity
Status: Active support from Synplicity
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Available Place and Route Tools
Xilinx ISE:
Advantages: Vendor provided Place and Route tool, there is no
other choice
Disadvantages: No point of comparison
Vendor: Xilinx
Status: Active support from Xilinx
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Synthesis With Synplify
add_file -vhdl -lib work accu.vhd
# Contraints and Options!
impl -add syn #implementation: "syn"
# Device Options
set_option -technology VIRTEX2;
set_option -part XC2V8000
set_option -package FF1517;
set_option -speed_grade -5
# Compilation/Mapping Options
set_option -top_module "accu";
set_option -default_enum_encoding onehot
set_option -resource_sharing 0;
set_option -symbolic_fsm_compiler 0
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Synthesis With Synplify
# Mapping Options
set_option -frequency 500.000;
set_option -disable_io_insertion 0
set_option -pipe 0;
set_option -modular 0;
set_option -retiming 0
# Output Options
set_option -write_verilog 0;
set_option -write_vhdl 1
set_option -write_apr_constraint 0 # Whether to output constraints
project -result_file "./accu.edf";
impl -active "syn" # Results
(Source: LEON2 synthesis scripts)
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Post-synthesis Simulation
Modelsim can be used
UNISIM libraries are needed and available with Modelsim
Vendor specic modules available from vendor tool or synthesis tool
distributions
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User Constraints File (UCF)
# Define Logical-to-Physical pin mapping
NET "LCLKA" LOC = "AG18";
# <> for FPGA Express and XST; () for Synplify
NET "RA<18>" LOC = "AG6";
# Define attributes
NET "RA0<*" FAST;
# Define setup, hold and other timing constraints for
# peripheral devices
TIMEGRP RAM_ADDR_PADS = "pads(RA<*>)";
TIMEGRP "RAM_PADS_ADDR" OFFSET = IN 5.0ns BEFORE "LCLKA";
TIMEGRP "RAM_PADS_ADDR" OFFSET = OUT 7.0ns AFTER "LCLKA";
NOTE: TIMESPEC syntax is more intuitive
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Place and Route with Xilinx ISE
# Convert to Xilinx Database Format
ngdbuild -nt on -dd work -uc accu.ucf -p XC2V3000-5-FF1152\
accu.ngd
# Map to target device
map -pr b -o accu_map.ncd accu.ngd accu.pcf
# Do Place and Route
par -w accu_map.ncd accu.ncd accu.pcf
# Timing Analysis
trce -e 3 -o accu.twr accu.ncd accu.pcf
# Final Bitfile Generation
bitgen -w -g drivedone:yes accu.ncd accu.bit
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Other Pecularities
Take care with array indices (<>, () or [])
If you are using coregen generated components, you should select the
correct synthesis tools
Automatic inferring of devices and retiming optimization makes
synthesis very time consuming
Simulation with device modules such as Virtex ChipStartup will take
very long
RAM models are available from vendors which you can directly use
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FPGA Synthesis, P&R Demo
Using the on-chip BlockRAMs
Using on-chip Digital Clock Managers (DCM)
Using clock-buffers
Interfacing to an external RAM
Specifying voltage level for output pins
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Complications Over FPGA Synthesis, P&R
Massive amounts of hardware edibility leads to complications and
advantages
Deciding parameters such as row utilization, chip aspect ratio etc.
requires insight and experience
Various stages of the ow are inter-dependent
Difficult to estimate the effects of various stages of ow early on
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Why STA?
Verify the design meets timing constraints • Faster than timing-driven, gate-level simulation •
Ease design debugging
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STA Compute Method
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Timing Paths
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Delay Calculation
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Synchronous Circuit Delay Calculation
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Path Measurements
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Constraint Checks
• Min/Max Delay
• Setup/Hold
• Recovery/Removal
• Clock Definitions
– Gated Clocks
– Clock Skews and Multiple Clock Groups
– Multi-frequency Clocks
– Multi-phase Clocks
• False Paths
• Multi-cycle Path Analysis
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Min/Max Delay
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Setup/Hold Basics
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Setup/Hold Checking for Flip-Flops
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PCB Requirements for Setup/Hold
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I/O Setup Analysis Example
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I/O Setup Analysis Example
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I/O Hold Analysis Example
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Hold Analysis Example
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Clock Definitions
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Polarity Skew
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Polarity Skew Analysis Example
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Phase Skew
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Phase Skew Analysis Example
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Phase Skew Analysis Example
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Frequency Skew
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Frequency Skew Analysis Example
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Frequency Skew Analysis Example
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Cycle Skew
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Cycle Skew Analysis Example
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False Paths
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Analysis of Phase-Locked Loops
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Timing Analysis By Stage
• Preliminary Timing Analysis
• Synthesis Timing Analysis
– RTL vs. Gate-Level
– Timing in RTL Code
– Black-Box Timing Arcs
• Place & Route Timing Analysis
– Post-Map
– Post-Placement
– Post-Route
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Timing Parameters
• Corners and STA
• Timing Derating Factors
• Grading FPGAs by Speed
• Best-Case Delay Values
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Synthesis STA with Precision
• Timing Specification
– Native or Synopsys (SDC) Format
• Analysis Commands
• Timing Report
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Synthesis STA with Synplify
• Timing Specification
– Native Synplify Design Constraints
• Analysis Commands
• Timing Report
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Place & Route STA with ispLEVER
• STA Setup, Project Navigator
• TRACE Report
• Routing Congestion with Design Planner
• Viewing Critical Paths with Design Planner
• I/O Timing Report
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Thank You
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