Clocking Strategies

1. Clocks in Digital Circuits

2. Registers and Latches: Operation with clocks
3. Setup and Hold Time and their effect on clocking
4. Clock skew and its effect
Clocking Strategies
 Digital circuits or VLSI design involves systems
based on
 Finite State Machines (FSM)
 Pipelining (Register based or Latch Based)

 In these systems
 clock is required for design.
 Referred as synchronous systems.

 Clock means timing analysis and constraints.

Systems based on Clock
 FSM Inputs
Combinational
Outputs

Logic

Latches or
Flip-Flops CLK

Inputs Outputs
Combinational Combinational
 Pipelining Logic Logic

CLK
Latches
 Latches – level sensitive wrt clock
 Low-level: Active for clock at logic level 0.
 High-level: Active for clock at logic level 1.

CLK

Q
Active Low

Q
Active High
Registers
 Registers – edge sensitive wrt clock
 Positive-Edge:Active for clock transition 0→1.
 Negative-Edge: Active for clock transition 1→0.

CLK

Q
Negative Edge

Q
Positive Edge
 Timing Requirements
 No transitions are ideal. Timing requirements to
be followed
Clk Period (tclk)
 Setup time (ts)
 Hold time (th) CLK
Setup Time (ts)
 Clock-Q Delay (tcq)
Time for which input should be stable before D
the arrival of active edge of the clock.
Hold Time (th)
Time for which input should be stable
after the arrival of active edge of the Q
clock. Negative Edge
Time after which the output is stable after Clock to Q Delay (tcq)
the arrival of the active edge of the clock.
Timing Constraints
 Timing requirements impose timing constraints
 Registers/ Latches (ts, th, tcq)
 Combinational Block (tcb)

 Decide the maximum operating frequency or

minimum clock period (tclk).
ts th tcq tcb ts th tcq

Combinational
Logic

CLK
FSM: Data Flow
Inputs Outputs
Combinational
Logic

CLK
CLK

Initial State S0 S0
loaded in the
register. S1
S2
S3
FSM: Setup Time Constraint
Outputs
tclk >= tcq + tcb + ts
Inputs
Combinational
Logic tclk >= tcq + tcbmax + ts

Defines the longest

tcb path delay constraint.
ts S2

S1 CLK tclk
tcq S1 CLK

S0

S1
S2
S3
 FSM: Hold Time Constraint
Outputs
tcq + tcb >= th
Inputs
Combinational tcq + tcbmin >= th
Logic

Defines the shortest

tcb path delay constraint.
S3

S2 CLK
S2 CLK
tcq

No disturbance until S0
the hold time th.
S1
S2
S3
 Pipeline Implementation
 Registers: edge triggered and therefore execution
is one stage per clock cycle.
 Latches: level triggered and therefore execution is
two stages per clock cycle.

R1 ts th tcq tcb R2 L1 ts th tcq tcba L2 ts th tcq tcbb L3

Combinational Combinational Combinational

Logic Logic A Logic B

CLK CLK
 Pipeline: Data Flow (Registers)
R1 ts th tcq tcb R2

Combinational
Logic

CLK
(tclk)
CLK

D2 D1 D0 D0
D0
D1
D2 D1
 Pipeline: Setup Time Constraint
R1 ts th tcq tcb R2 tclk >= tcq + tcb + ts
Combinational
Logic
D0
tcq
D0 tcb D0 ts
tclk >= tcq + tcbmax + ts

CLK
(tclk) Defines the longest
tclk path delay constraint.
CLK

D2 D1 D0 D0
D0
D1
D2 D1
 Pipeline: Hold Time Constraint
R1 ts th tcq tcb R2
D0 No disturbance
Combinational until th
Logic
D1 tcq D1 tcb D1 tcq + tcb >= th

CLK
(tclk) tcq + tcbmin >= th
CLK
Defines the shortest
path delay constraint.
D2 D1 D0 D0
D0
D1
D2 D1
 Pipeline: Data Flow (Latches)
L1 ts th tcq tcba L2 ts th tcq tcbb L3

Combinational Combinational
Logic A Logic B

CLK
(tclk)

D0 CLK
D1
D0
D2
D0
D1 D0
D1 D1
D2
 Pipeline: Data Flow (Latches)
tc1>= tcq + tcba + ts D1 tcq tc2>= tcq + tcbb + ts
L1 ts th tcq tcba L2 ts th tcq tcbb L3
D1
Combinational Combinational
Logic A Logic B
D0 D0 D0 D1
tcbb ts
tcq ts
CLK tcba
(tclk)

D0 tc2
CLK
tc1
D1
D0
D2
D0
D1 D0
D1 D1
D2
tclk = tc1+ tc2>= 2(tcq + ts) + tcba + tcbb
 Timing in Latches
 Alternate latches have same timing with respect
t
to clock. nonoverlap
tclk
φ1
 Clocks in Latches φ2
 Two-phase clock (non-overlapping). tclk/2
 Narrow pulse clock signals. tclk
φ1/φ2
tpw

L1 L2 L3

Combinational Combinational
Logic A Logic B

φ1 φ2 φ1
Clock Skew
 Clock reaches at different points at different
instances.
 Depending on the data flow and the clock
signals
 Negative Skew: Data and clock move in opposite
directions, destination is clocked before source.
 Positive Skew: Data and clock move in same
directions, source is clocked before destination.
Clock Skew
Data Flow
 Negative Inputs Outputs
Skew Combinational
Logic
Combinational
Logic

CLK
Clock Flow

Data Flow

 Positive Inputs
Combinational Combinational
Outputs

Skew Logic Logic

CLK
Clock Flow
 Negative Clock Skew
 Affects the setup time constraint.
R1 ts th tcq tcb R2 tclk >= tcq + tcb + ts
Combinational tclk >= tcq + tcbmax + ts
Logic
tsrc D0 tcq
D0 tcb D0 ts
(tdes + tclk)
CLK
(tclk)
tclk
CLK
tdes + tclk >= tsrc + tcq + tcb + ts
tsk = tsrc - tdes
D0 D0
D0 tclk >= tcq + tcbmax + ts + tsk
max(tsk) <= tclk – (tcq + tcbmax + ts)
 Positive Clock Skew
 Affects the hold time constraint.
R1 ts th tcq tcb R2
D0 No disturbance
Combinational until th
Logic
D1 tcq D1 tcb D1 tdes
tcq + tcb >= th

CLK tsrc
(tclk) tcq + tcbmin >= th
CLK
tsrc + tcq + tcb >= th + tdes

D1 D0 D0 tsk = tdes - tsrc

D0 max(t ) <= t + t
D1 sk cq cbmin - th
Design with Clocking
 Setup and hold time constraints.
 Restrict the minimum clock period.

 Timings issues with latches and registers.

 Effect of Clock skew.

 Designer should avoid

 Timing violations (setup & hold time).

 Clock distribution (minimization of clock skew).

 Account for clock skew (clock skew budget).

Thank You