VHDL - Introduction

VHDL - Introduction
• Syllabus
• The VHDL – Hardware Description Language:
• Design Flow
• Program Structure
• Topics to be discussed
• Digital system design approaches: Top – Down approach verses Bottom – Up
Approach
• Design using HDLs
• What is VHDL
• Brief history of VHDL
• Role and features of VHDL
• VHDL vs Verilog
VHDL – Introduction: Modelling Digital Systems
• Digital systems:
• Range of systems from low-level components to complete system-on-a-chip
and board-level designs
• Humanly impossible to comprehend high level of complex systems in their
entirety.
• Thus need to find methods of dealing with the complexity, so that we can design
components and systems that meet their requirements, with some degree of
confidence.
• The most important way of meeting this challenge is to adopt a systematic
methodology of design.
• we start with a requirements document for the system, and design an abstract
structure that meets the requirements.
VHDL – Introduction: Modelling Digital Systems
• Then decompose the abstract structure into a collection of components that
interact to perform the same function.
• Each of the components can be in turn decomposed until we get to a level where
we have some ready-made, primitive components that perform a required
function.
• The result of this process is a hierarchically composed system, built from the
primitive elements.
• The advantage of this methodology is that each subsystem can be designed
independently of others.
• When we use a subsystem, we can think of it as an abstraction rather than having
to consider its detailed composition. So at any particular stage in the design
process, we only need to pay attention to the small amount of information relevant
to the current focus of design.
VHDL – Introduction: Modelling Digital Systems
• Thus an model of digital system should have the following characteristics:
• Expressing system requirements in a complete and unambiguous way.
• Documenting the functionality of a system.
• Testing a design to verify that it performs correctly
• Formally verifying properties of a design.
• Synthesizing an implementation in a target technology (e.g., ASIC or FPGA)
• Thus the goals of modeling a digital system are:
• Achieve maximum reliability in the design process for minimum cost and
design time.
• Ensure that requirements are clearly specified and understood.
• Subsystems are used correctly.
• Designs meet the requirements
VHDL – Introduction: Hardware/ software design flow
VHDL – Introduction: Digital System Design

Flow Graph, Pseudo Code, ...

Bus & Register Structure

Gate Wire-list, Netlist

Transistor List, Layout, ...

 VHDL – Introduction: Using CAD tools to design circuits

• Computer-Aided Design (CAD) tools have become essential to the

design of digital circuits.
• Design entry
• Schematic capture – graphic entry of circuit elements
• Hardware description languages and circuit synthesis
• Two major languages – VHDL and Verilog
• Simulation
• Functional simulation – verify logical correctness
• Timing simulation – verify that performance goals are met
• Timing analysis
• Analysis of delays in circuit components and wiring to
• Verify that timing constraints are satisfied
VHDL – Introduction: Simplified CAD Tool Flow
 VHDL – Introduction: Digital System Design Approaches
Top – Down approach Vs Bottom – Up approach
• The different design levels in digital system design is
 VHDL – Introduction: Digital System Design Approaches
Top – Down approach Vs Bottom – Up approach

Top – Down
Approach
Top – Down
Approach Bottom – Up
Approach
VHDL – Introduction: Digital System Design Approaches
Top – Down approach Vs Bottom – Up approach
Top – Down Approach Bottom – Up Approach
Decomposition based Connecting of primitive blocks
What we are building How do we build it
Controls complexity Focuses on details
Starts with black box view and The design needs complete
then details are added for each detailed knowledge of what we
refrainment are designing
Over heads may be added to Optimized design is possible
the design
 VHDL – Introduction: Design using HDLs

• Why to use HDLs for modelling:

• In software everything is sequential
• Sequence of statements is significant, since they are executed in that order
• In hardware events are concurrent, so a software language cannot be used for
describing and simulating hardware.
• Advantages of Using HDLs to Design FPGAs
• Top-Down Approach for Large Projects
• Functional Simulation Early in the Design Flow
• Automatic Conversion of HDL Code to Gates
• Type Checking
• Early Testing of Various Design implementations
VHDL – Introduction: What is VHDL

VHDL is the VHSIC (Very High Speed Integrated

Circuit) Hardware Description Language

A Simulation Modeling Language

A Design Entry Language

A Standard Language

A Netlist Language
 VHDL – Introduction

• Two HDLs are widely used

• VHDL
• Verilog
• VHDL is a hardware description language which uses the syntax of ADA. Like
any hardware description language, it is used for many purposes.
• For describing hardware.
• As a modeling language.
• For simulation of hardware.
• For early performance estimation of system architecture.
• For synthesis of hardware.
• For fault simulation, test and verification of designs.
 VHDL – Introduction: Brief history
• 1981 : Department of Defense, USA launches the .Very High Speed Integrated
Circuits. (VHSIC) project.
• 1983 : Request for Proposal (RFP) issued by US Air Force to develop a language for
hardware design description. The winner was a team composed of Intermetrics, IBM
and TI.
• 1985 : VHDL version 7.2 made available.
• 1986 : Initial suite of support software released. IEEE starts effort of standardizing
VHDL.
• 1987 : IEEE-1076 Standard released, VHDL-87.
• 1987: Mil Std. 454 requires comprehensive VHDL descriptions to be delivered with
ASICs
• 1993 : Revised IEEE-1076 Standard released, VHDL-93.
• 2001 : Revised IEEE-1076 Standard released, VHDL-2001.
• 2002 : Work on VHDL-200x started.
 VHDL – Introduction: Role and Features of VHDL

• For design specification

• For design capture
• For design simulation
• For design documentation
• As an alternative to schematics
• As an alternative to proprietary languages
 VHDL – Introduction: VHDL vs Verilog
• Both are Hardware description languages.
• They are each a notation to describe the behavioral and structural aspects of an
electronic digital circuit.
• VHDL is older one and based on ADA(Activity Discard Acknowledgment /
Automatic Data Acquisition (programming language)) and PASCAL.
• Verilog generally follows c-programming language. Developed by Gateway
Design Automation (1980), Later acquired by Cadence design(1989) who made it
public in 1990. Became a standardized in 1995 by IEEE (Std. 1364) regulated by
Open Verilog International (OVI)
• VHDL is case insensitive whereas Verilog is case sensitive.
• VHDL is strongly typed language (A strongly typed language like VHDL does not
allow the intermixing, or operation of variables, with different classes) whereas
Verilog is weakly typed language.
 VHDL – Introduction: VHDL vs Verilog
• VHDL is harder to learn when compared to Verilog.
• VHDL supports user defined data types also whereas Verilog supports only
predefined data types.
 VHDL – Introduction: VHDL vs Verilog
• VHDL supports Multiple design-units (entity/architecture pairs), that reside in the
same system file, may be separately compiled if so desired.
• The Verilog language is still rooted in it's native interpretative mode. Compilation
is a means of speeding up simulation, but has not changed the original nature of
the language. As a result care must be taken with both the compilation order of
code written in a single file and the compilation order of multiple files. Simulation
results can change by simply changing the order of compilation.
• In VHDL. Procedures and functions may be placed in a package so that they are
avail able to any design-unit that wishes to use them.
• There is no concept of packages in Verilog. Functions and procedures used within
a model must be defined in the module. To make functions and procedures
generally accessible from different module statements the functions and
procedures must be placed in a separate system file and included using the
`include compiler directive.
 VHDL – Introduction: VHDL vs Verilog
• Verilog has the same advantage in availability of simulation models.
• Verilog has a PLI that permits the ability to write parts of the code using other
languages.
• VHDL has higher-level design management features (configuration
declaration, libraries).
• VHDL and Verilog are identical in function and different in syntax
• There are more constructs and features for high-level modeling in VHDL than
there are in Verilog
• VHDL allows concurrent procedure calls; Verilog does not allow concurrent task
calls.
• VHDL uses The generate statement to replicate a number of instances of the
same design-unit or some sub part of a design, and connects it appropriately.
• The choice of HDL is not to be based on technical capability, but on: personal
preferences, EDA tool availability and commercial, business and marketing issues
 VHDL vs Verilog
VHDL Verilog
Multiple design-units (entity/architecture Care must be taken with both the
pairs), that reside in the same system file, compilation order of code written in a
may be separately compiled if so desired. single file and the compilation order of
multiple files.
A multitude of language data types can Simulation results can change by simply
be used. changing the order of compilation.
User defined data types are available NO user-defined data types
Very strongly typed Compared to VHDL, Verilog data types
are very simple, easy to use. There are
net data types example wire, reg
Three constructs : Procedures, Functions Two constructs: Functions and Tasks
and Packages
 VHDL vs Verilog
VHDL Verilog
They can be placed in a package so that There is no concept of packages in
they are available to any design unit that Verilog.
wishes to use them.
There are many ways to model the same Verilog is probably the easiest to grasp
circuit, specially those with large and understand.
hierarchical structures.
There are more constructs and features Except for being able to parametrize
for high-level modelling in VHDL than models by overloading parameter
there are in Verilog. constants, there is no equivalent to the
Package high-level VHDL modelling statements
Configuration in Verilog
Generate
Generic
 VHDL vs Verilog
VHDL Verilog
A library is a store for compiled entities, There is no concept of a library in
architectures, packages and configurations Verilog
Simple two input logical operators are The Verilog language was originally
built into the language, they are: NOT, developed with gate level modelling in
AND, OR, NAND, NOR, XOR and mind, and so has very good constructs
XNOR. for modelling at this level and for
modelling the cell primitives of ASIC
and FPGA libraries.
Any timing must be separately specified Verilog is more like C because it's
using the after clause constructs are based approximately 50%
on C and 50% on Ada.
VHDL is a concise and verbose language;
its roots are based on Ada