COS

Workshop software development on

Linux

gmake

Workshop Software development on Linux

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Objectives

At the end of this module you will be able to:

• decide when to use gmake
• read existing Makefiles
• write Makefiles using:
– different types of rules
– different types of variables
– shell commands
– conditional statements
– built-in functions
– your own functions

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Contents
• what is gmake?
• basic definitions
• rules and command basics
• line continuation
• variables
• commands, shell
• conditional statements
• advanced rules
• functions

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Introductory example
• Manually compiling a file
cc helloworld.c -o helloworld
– Up to date? An include file may have changed. Recompile to be sure?

• Write a Makefile
helloworld : helloworld.c
cc helloworld.c -o helloworld
• Run gmake
gmake output on screen: cc helloworld.c -o helloworld
• Run gmake again
gmake output on screen: gmake: helloworld is up to date.
• A shorter version of this Makefile
helloworld :

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What is gmake?
• Gmake is a tool that helps to (re)build software
– Building in this context mostly means: compiling, linking, installing,...

• In a Makefile you describe when and how to rebuild files

– when called, gmake reads this Makefile and rebuilds files if needed

• Gmake has built-in rules for translating files of many types

– file types are recognised by the suffix in the filename. '.c' -> C-file
– You may shorten your Makefile descriptions, relying on these rules
• Gmake only rebuilds files 'out of date'
– if a source file changes, it is newer than its object. For gmake, this
means the object is out of date, so gmake will recompile the source.
• Gmake is especially useful for maintaining software consisting
of several source/include files
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Gmake achieves no miracles...
• You have to write your own source code
– C, C++, java, tex, ...

• You have to organize your code into files, choose proper

filenames, create a directory structure
– source and include files in 1 directory, or separate them?
– put sources for a library in a different directory or not?

• You have to think of how and where you want to

generate files like object files, executables
– which compiler flags are needed?
– object files in separate directory? (easy to clean up later)
– If you write this in a Makefile, you have to think only once...

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Make implementations, documentation
• Many make implementations exist
– Apart from make, there is amake, bmake, ... zmake, and more
• Gmake (GNU-make) is the default on Linux
– On Linux, /usr/bin/gmake is the same as /usr/bin/make
• Gmake can also be installed with cadenv
– On the NatLab, gmake is available on all UNIX-platforms
• For further reference and more details see:
– the manual: http://www.gnu.org/software/make/manual/make.html
– "Managing projects with GNU make" O'Reilly (ISBN 0-596-00610-1)
– Useful info, white papers: http://make.paulandlesley.org
• Paul's Rules of Makefiles (Paul Smith, gmake maintainer)
• Multi-Architecture Builds Using Gmake
• Advanced Auto-Dependency Generation
• How NOT to use VPATH

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Contents
• what is gmake?
• basic definitions
• rules and command basics
• line continuation
• variables
• commands, shell
• conditional statements
• advanced rules
• functions

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Basic definitions
• Gmake needs a description file called the Makefile
– You can use a different name: gmake -f othername [target]...
• A Makefile should contain one or more rules
– It may contain also: variable definitions, functions,
directives, comments
• Rule syntax:
target [target ...] : [prerequisite ...]
[<TAB> command line] ...

• A target is a file we want gmake to (re)build

– If a target needs updating, its command lines are executed
• A prerequisite is a file the target depends on
– A prerequisite is often called a dependency
– The prerequisites have to be up to date before gmake starts building
the target. If they are not, gmake updates them first
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Makefile example: targets & prerequisites
comment lines start with '#'

a colon (:) is needed as an

end-of-target-list sign

first (=default) target

single target
prerequisites
multiple targets

target without prerequisite

• The targets and prerequisites in this example reflect real files,

except target all. Such a target is called a phony target. More
about that later...

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Special targets
Gmake has a number of special built-in targets
• Built-in target names start with a '.'
– e.g.: .PHONY, .SUFFIXES, .IGNORE

• The .PHONY target

– Targets that do not reflect real files ('all', 'clean',...) should be
declared phony by making them prerequisites of target .PHONY
e.g.: .PHONY: all clean install ...

• The .SUFFIXES target

– You can add new file types with a new suffix:
.SUFFIXES: .q .z .myridiculouslylongsuffix
– you can delete all known suffixes first by not specifying a suffix:
.SUFFIXES:

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Dependency tree: to be or not to be up to date
• A file A depends on file B if B is needed to create A
– e.g., a C-compiler needs program.c to create program.o,
so program.o depends on program.c (at least!)
• A file may depend on several files, each depending on
other files,... This hierarchy is called a dependency tree
• A target is up to date if its dependency tree is, so if:
– the target exists as a file, and
– the target is newer than its prerequisites, and
– the prerequisites are up to date
• If you run gmake [target]
– gmake updates the target's dependency tree (if needed)
– updating order is from the leaves up to the root

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Dependency tree: example

all

myprogram prog1 prog2

myprogram.o prog1.o prog2.o

myprogram.c myprogram.h prog1.c prog.h prog2.c

• Suppose we run gmake myprogram

gmake will check and update in the following order:
– are myprogram.c and myprogram.h up to date? (we assume yes)
– is myprogram.o up to date (newer than .c and .h)? If not, update first.
– is myprogram up to date (newer than myprogram.o)? If not, update.
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Contents
• what is gmake?
• basic definitions
• rules and command basics
• line continuation
• variables
• commands, shell
• conditional statements
• advanced rules
• functions

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Rules and command basics
• If a target is not up to date, gmake will update it by running
the command lines you specified for it in the Makefile
• Command lines MUST start with a <tab> character!!!!
• For each command line, gmake starts a new 'shell'
– So, this command line can be a shell script!

• In explicit rules (rules with target names written in full),

you don't always have to specify commands
• If you don't specify a command for a target, gmake tries to
use a command from its internal knowledge base
example: gmake has a built-in rule on how to compile C-sources.
If a target with suffix '.o' depends on a file with suffix '.c', gmake
would use (roughly) "cc file.c -c -o file.o".

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Makefile examples: from explicit to implicit

leading <tab> character!!!

rules

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Contents
• what is gmake?
• basic definitions
• rules and command basics
• line continuation
• variables
• commands, shell
• conditional statements
• advanced rules
• functions

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Line continuation
• A group of lines will be joined into 1 single line if these lines
(except the last one) end with the '\' character
– You can use this for example if a target has so many
prerequisites that they wouldn't fit on one line
– More often, it is used to assign (lots of) file names
to a gmake variable. (Later in this workshop)
– You can also use it to combine several command lines,
and have them executed by the shell in one go
– This way, you can put multi-line shell scripts in your Makefile

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Contents
• what is gmake?
• basic definitions
• rules and command basics
• line continuation
• variables
• commands, shell
• conditional statements
• advanced rules
• functions

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Variables
• There are 2 flavors of variables. They differ in:
– how values are assigned (with '=' or ':=')
– the way they will expand

• Of both flavors, the value is obtained by $(varname)

$(program) : $(objects)
cc -o $(program) $(objects)
– if you don't use brackets, gmake assumes a 1-letter variable.
e.g. $x  $(x) is okay, but $objects  $(o)bjects probably not!
• A new (different type) assignment will change the flavor
of the variable. Not recommended.
• All environment variables except SHELL are inherited.
– e.g. you can use $(HOME)
– do you want the Makefile to rely on environment variables?
• Make variables often are called macros
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Recursively expanded variables
This type of variable (flavor 1) is created by: var = value
• Implemented by most versions of make (not only gmake)
• Verbatim text assignment (assignment without expansion)
eg: myvar = foo $(myvar) bar
• Expanding is postponed
– Suppose we define: var1 = $(var2), var2 = $(var3), var3 = Done!
The command echo $(var1)
will echo Done!
because it expands recursively: $(var1)  $(var2)  $(var3)  Done!
– a real life example:
CFLAGS = $(include_dirs) -O
include_dirs = -Idir1 -Idir2 # as example defined after CFLAGS!!
cc $(CFLAGS) myprogram.c  cc -Idir1 -Idir2 -O myprogram.c
• The following would cause an infinite loop!! (detected by gmake):
CFLAGS = $(CFLAGS) -O
• To append text without expanding, use '+='
CFLAGS += -O

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Simply expanded variables
This type of variable (flavor 2) is created by: var := value

• Expanding is direct
Suppose we define:

x := oldtext
y := $(x) extrastuff
x := newtext

The command echo $(y)

will echo oldtext extrastuff
Using flavor 1 assignments, it would echo newtext extrastuff

• Because of expanding values directly, the following DOES work:

CFLAGS := $(CFLAGS) -O

• The simply expanded variables are easier to use, more predictable

and more time-efficient, but less portable

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Predefined variables
• Lots of predefined variables are used in implicit rules
There are 2 main groups:
Program variables (a few examples):
– CC to compile C programs; default cc
– CPP to run the C preprocessor; default $(CC) -E
– CXX to compile C++ programs; default g++
– TEX to 'compile' tex into DVI; default tex
Program flag variables:
– CFLAGS extra flags to give to the C compiler
– LDFLAGS extra flags to give to the compiler during linking
example: $(CC) $(CFLAGS) myprogram.c -c -o myprogram.o
• You may override the values of these variables
example: CC = gcc, CFLAGS += -Wall -g ...
and again: $(CC) $(CFLAGS) myprogram.c -c -o myprogram.o

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Automatic variables
• Automatic variables are computed dynamically, based
on target or prerequisite names of an activated rule
– $@ The name of the (current) target of the activated rule
– $< The name of the first prerequisite
– $? The names of prerequisites newer than the target
– $^ The names of all prerequisites
These vars. can have different meanings in other make flavors!!
• You can combine the previous variables with 'D' or 'F'
– $(@D) = Directory of $@
– $(@F) = File name of $@
• Now we can understand the command gmake uses
by default to compile C files into object files:
$(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

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Contents
• what is gmake?
• basic definitions
• rules and command basics
• line continuation
• variables
• commands, shell
• conditional statements
• advanced rules
• functions

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Commands, shell (1)
• Default, gmake passes command lines on to /bin/sh
• If a command contains a '$' that should be interpreted by
the shell, the '$' must be escaped by an extra '$'
eg: cd $$DIR (one $:  cd $DIR  cd $(D)IR  cd ??IR )
• Previous shell settings will be lost in a new shell!

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Commands, shell (2)
• You can overrule the shell being used by gmake, by setting
the variable SHELL, eg: SHELL = /bin/ksh.
– think carefully about portability before you do this!
• Gmake will echo the command line it executes.
To suppress echoing, precede the command line with '@'.
• If a command returns an error, gmake stops processing. To
ignore the error, precede the command line with '-'.

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Contents
• what is gmake?
• basic definitions
• rules and command basics
• line continuation
• variables
• commands, shell
• conditional statements
• advanced rules
• functions

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Conditional statements: types and usage
• A conditional statement causes part of the makefile to be
'seen' if true or to be ignored if false.
• Gmake has 4 types of conditionals:
ifeq (str1,str2) true if strings are equal
ifneq(str1,str2) true if strings are not equal
You may use variable references in strings
ifdef variable true if variable has non-empty value
ifndef variable true if variable undefined/empty
Note that in if(n)def, a variable is not expanded to see if it's empty.
So, if we define foo = $(bar)
ifdef foo is true, even if bar is undefined!
• All types of conditionals:
– can be used with or without else part
– have to end with endif
– can be nested
– may be indented by blanks. Don't use tabs!
• Be careful when checking unset/empty variables
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Conditional statements: example

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Contents
• what is gmake?
• basic definitions
• rules and command basics
• line continuation
• variables
• commands, shell
• conditional statements
• advanced rules
• functions

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Pattern rules
A pattern rule contains the character '%' in the target
– Such a target name is a pattern for matching file names
– The character '%' can match any non-empty string
– All other characters in the target pattern match literally. Example:
%.o :
@echo making target $@
Running gmake main.o would echo making target main.o

– '%' may also be used in the prerequisites, as a place holder for the
string matched by '%' in the current target. As example, the rule to
build an object file in the same directory as its C-file:
%.o : %.c
$(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

gmake /tmp/myprog.o would check/compile /tmp/myprog.c

– A pattern rule will only be applied if no explicit target matches, or no
commands were specified for such an explicit target
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Implicit rules, rule order
• implicit rule: rule without explicit (full) target names
– Pattern rules are the most important kind of implicit rules
– Suffix rules are another kind of implicit rules. Still in gmake for
compatibility reasons
– Implicit rules you write overrule the built-in implicit rules
– Implicit rules are applied by gmake when:
• other matching rules don't specify commands.
• no explicit rules exist that match the target
example Makefile:
special.o: special.c special.h  explicit rule
$(CC) $(SPECIALFLAGS) $< -c -o $@
%.o : %.c  implicit (pattern) rule
$(CC) $(CFLAGS) $< -c -o $@
Only gmake special.o would cause a match by the explicit rule
gmake xxx.o would cause a match by the implicit rule
– Matching order is from more to less explicit
• E.g, having rule %.o : and rule % : file.o would match %.o, not %

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Contents
• what is gmake?
• basic definitions
• rules and command basics
• line continuation
• variables
• commands, shell
• conditional statements
• advanced rules
• functions

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Using functions
• A built-in function is called like:
– $(function) - the call resembles a variable reference
– $(function arg) - 1 argument, no comma!
– $(function arg1,arg2,...) - arguments, comma separated
– Arguments can contain text, variable references or function calls
• The textual result of the function is substituted into the
makefile at the point of the call (again like a variable)
• Function calls can be nested
examples

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Built-in functions
• Gmake has many built-in functions. A few of them:
– $(subst str1,str2,text) in text, replace str1 by str2
– $(findstring string,text) return string if found in text
– $(wildcard shell pattern) return file names matching pattern
– $(shell shell command) execute shell command

• For the subst() or patsubst() function, an often used

shortcut exists, the substitution reference.
– syntax: $(var:endstr1=endstr2)
– meaning: in every word contained by var and ending with endstr1,
substitute endstr1 by endstr2. An example:

objects := a.o b.o ... z.o

sources := $(objects:.o=.c)

This sets sources to a.c b.c ... z.c

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Writing functions
• Writing functions is like defining variables:
– myfunction = text
• Calling syntax: $(call myfunction, param1, param2,...)
– The parameters in $(call ...) are passed to myfunction.
– In text of myfunction, you can refer to them by using $1,$2,...
– Example: reverse = $(2) $(1) # use '=', NOT ':='
revargs := $(call reverse,foo,bar)
The return value of reverse in this call expands to 'bar foo'.
• A 'real life' example:

easy, after
the scripting
workshop;-)

function definition

function call

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Additional information

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Including makefiles
• You can include other makefiles in your Makefile
– e.g. you have a generalized Makefile, the only things that change are
some settings. Put these settings in a file say Makefile.settings
In your Makefile you could write:
include Makefile.settings
it's an error if the file does not exist. Gmake will stop
-include Makefile.settings
the '-' suppresses errors/warnings. Gmake tries to continue
– The included files will be considered part of the Makefile
• Including dependency makefiles
– An include file often includes other include files including others,...
An object file depends on its source file and all these include files.
You can generate these dependencies automatically, by using
special compiler options, e.g.: $(CC) -M $(INCLUDE) and write them
to separate makefiles (de facto source name with suffix .d).
Now include the makefiles, e.g.: -include $(SOURCES : .c = .d)
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Not treated in this workshop
• VPATH
– can be used to specify directories where make should look for
source files. Works best if make is called in the directory where
the objects shoud be generated. (read white paper Paul Smith)
• double colon rules: target :: prereq
– According to the GNU manual, not often useful
– Be aware that the meaning changes, depending on usage in
explicit or implicit rules!!! In implicit rules, a :: rule is terminal
• static pattern rules
– targets are explicit,
a pattern is added to use a common substring
• SUFFIX rules
– more obscure than pattern rules, but common in old makefiles
– order of suffixes reversed: .c.o equivalent to %.o : %.c

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