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Chapter 3.2 Arthemetic and Logic Instruction Instruction Set

This document discusses various arithmetic, logic, and shift instructions for the 8086 microprocessor. It covers addition, subtraction, multiplication, division, logical AND, OR, XOR, and NOT operations. Shift and rotate instructions are also described. Examples are provided for each instruction type to illustrate their syntax, algorithms, operands, and how they affect processor flags. BCD adjustment instructions are also covered.

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76 views

Chapter 3.2 Arthemetic and Logic Instruction Instruction Set

This document discusses various arithmetic, logic, and shift instructions for the 8086 microprocessor. It covers addition, subtraction, multiplication, division, logical AND, OR, XOR, and NOT operations. Shift and rotate instructions are also described. Examples are provided for each instruction type to illustrate their syntax, algorithms, operands, and how they affect processor flags. BCD adjustment instructions are also covered.

Uploaded by

sagni
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Department of Electrical and computer Engineering

College of Engineering and Technology


Jimma University
Be familiar with the 8086
microprocessors instruction sets
 Data transfer instruction
Arithmetic and logic
instruction
 Program control and interrupt
instruction

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Arithmetic instructions
 Addition
 Subtraction
 Multiplication
 Division
 BCD and ASCII arithmetic
instruction
Basic logic operation
 AND, OR, NOT, XOR
Shift and Rotate instruction
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 Syntax:- ADD Destination, source
 Algorithm:- destination = destination + source
 Where (Destination , source combination)

 Flag affected

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 Syntax:- ADC Destination, source
 Algorithm:-destination = destination + source + cf
 Where (Destination , source combination)

 Flag affected

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 The source and destination can not be both
memory
 Both source and destination must be the
same size (Both word and byte)

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 Syntax:- INC Destination
 Algorithm:-destination = destination + 1
 Where destination can be

 Flag affected

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 Syntax:- SUB Destination, source
 Algorithm:- destination = destination - source
 Where (Destination , source combination)

 Flag affected

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 They are special types of subtraction (dec)
instruction
 Syntax: dec operand
 Where operand can be register or memory
 Function:sub 1 from operand
 Algorithm operand= operand – 1

 MOV AL,4
 DEC AL

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 Mul (Unsigned multiplication)
 Syntax:- mul operand
 Algorithm:-

 where opernd can be

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 Syntax:- imul operand
 Where operand can be
 Algorithm (what it does)

 Example

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 Div(unsigned division instruction)
 Syntax:- DIV operand
 Where operand can be
 Algorithm

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 Syntax:- idiv operand
 Where operand can be:-
 Algorithm:-

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 BCD Arithmetic
 DAA(decimal adjust after addition )
 DAS (Decimal adjust after subtraction)
 Syntax DAA (no operand)
 Function:-
 Corrects the result of addition of two packed
BCD values
 Algorithm

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 Syntax:-DAS (no operand)
 Function:
 Corrects the result of subtraction of two packed
BCD values. It only work for AL registers
 Algorithm

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 DAS

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 AAA (Ascii adjust after addition)
 Function:
 Corrects result in AH and AL after addition when
working with BCD values.

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 Algorithm:-

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AAS (ascii adjust after sub..)
Aam (ascii adjust after
mul..)
AaD (ascii adjust before
div..)

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add ax, bx ;axax+bx and set flags
adc ax, bx ;axax+bx+CF and set flags
inc ax ;axax+1 and set flags
aaa ;ASCII Adjust after Addition
daa ;Decimal (BCD) Adjust after Addition
sub ax, bx ;axax-bx and set flags
dec ax ;axax-1
das ;Decimal (BCD) Adjust after Subtraction
aas ;ASCII Adjust after Subtraction
mul cx ;dx:ax ax * cx (unsigned)
imul cx ;dx:ax ax * cx (2’s complement)
div cl ;alax/cl Quot. AND ahax/cl Rem.
idiv cx ;ax(dx:ax)/cx Quot. AND dx  Rem.
 Included in this groups of instruction are
 AND,
 OR,
 XOR,
 NOT and
 TEST(which is a kinds of And
operator)

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 Syntax: AND operand1, operand2
 Where OP1, op2 combination can be

 Function: Logical AND between all bits of two


operands. Result is stored in operand1
 Algorithm

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 Syntax: or operand1, operand2
 Where op1,op2 combination can be

 Function:-Logical OR between all bits of two


operands. Result is stored in first operand.
 Algorithm:

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 Syntax: xor operand1, operand2
 Where op1,op2 combination can be

 Function:-Logical XOR (Exclusive OR)


between all bits of two operands. Result is
stored in first operand
 Algorithm:

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 Syntax: not operand
 Where op1,op2 combination can be

 Function:-Invert each bit of the operand.


 Algorithm:

 No flag is affected

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 Syntax: test operand1, operand2
 Where op1,op2 combination can be

 Function:- Logical AND between all bits of


two operands for flags only. These flags are
effected: ZF, SF, PF. Result is not stored
anywhere.
 Algorithm:

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shl - Logical Shift Left
CF REG 0

shr - Logical Shift Right


0 REG CF

sal - Arithmetic Shift Left (same as logical)


CF REG 0

sar - Arithmetic Shift Right (sign bit is preserved)

REG CF
MSB

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rol - Rotate Left
CF REG

rcl - Rotate Through Carry Left

CF REG

ror - Rotate Right


CF REG

rcr - Rotate Through Carry Right

CF REG

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BITWISE LOGICAL
not ax ;1’s Complement-Logical Invert
and ax, bx ;Bitwise logical and operation
or ax, bx ;Bitwise logical inclusive-or operation
xor ax, bx ;Bitwise logical exclusive-or operation
test ax, fffh ;Bitwise and but result discarded

SHIFT
shl ax, 4 ;Logical shift left
sal ax, 3 ;Arithmetic shift left
shr ax, 4 ;Logical shift right
sar ax, 3 ;Arithmetic shift right

ROTATE
rol bx, 3 ;Rotate left
ror cx, 4 ;Rotate right
rcl ax, 1 ;Rotate left through carry
rcr dx, 6 ;Rotate right through carry

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