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DC Biasing of MOSFET

This document discusses different biasing circuits used for MOSFETs, including depletion-type, enhancement-type, voltage divider, and feedback biasing. For each biasing circuit, it outlines the key steps to determine the quiescent (Q-) point: 1) plot the transfer curve, 2) plot a line using circuit equations, 3) find where the line and curve intersect which is the Q-point, 4) use the Q-point values to solve for other circuit variables. It also notes that p-channel MOSFET biasing uses the same process but with reversed polarities from n-channel MOSFETs.

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Chilton Fernandes
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728 views13 pages

DC Biasing of MOSFET

This document discusses different biasing circuits used for MOSFETs, including depletion-type, enhancement-type, voltage divider, and feedback biasing. For each biasing circuit, it outlines the key steps to determine the quiescent (Q-) point: 1) plot the transfer curve, 2) plot a line using circuit equations, 3) find where the line and curve intersect which is the Q-point, 4) use the Q-point values to solve for other circuit variables. It also notes that p-channel MOSFET biasing uses the same process but with reversed polarities from n-channel MOSFETs.

Uploaded by

Chilton Fernandes
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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DC Biasing of MOSFET

Chilton Fernandes
Assistant Professor
SRIEIT
D-Type MOSFET Bias Circuits
• Depletion-type
MOSFET bias circuits
are similar to those
used to bias JFETs.
The only difference is
that depletion-type
MOSFETs can operate
with positive values of
VGS and with ID values
that exceed IDSS.

2
Voltage-Divider Bias
Step 1
Plot the transfer curve using IDSS, VP and
calculated values of ID. Using Shockley’s
Equation

Four points: A (0,IDSS)


B (Vp, 0)
C (Vp/2, IDSS/4)
Fourth point is calculated for VGS exceeds the
0V or more positive values.

Step 2
To plot a line we have to apply KVL to the
input loop which gives equation as
But we need to find VG using

Plot line for


• VGS = VG, ID = 0 A
• ID = VG/RS, VGS = 0 V 3
Voltage-Divider Bias
Step 3
The Q-point is located where the line
intersects the transfer curve is. Use the ID at
the Q-point to solve for the other variables in
the voltage-divider bias circuit.
Applying KVL to the output loop

These are the same steps used to analyze


JFET voltage-divider bias circuits.

4
When RS change…the linear characteristics will change..
1. Plot line for VGS = VG, ID = 0 and ID = VG/RS, VGS = 0
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q-point.
Use the ID at the Q-point to solve for the other variables in the voltage-divider bias circuit.
These are the same calculations as used by a JFET circuit.

5
Enhancement-Type MOSFET
The transfer characteristic for the enhancement-type MOSFET is very different from that
of a simple JFET or the depletion-typeMOSFET.

6
• Transfer characteristic for E-MOSFET

I D  k (VGS  VGS (Th ) ) 2

and
I D ( on )
k
(VGS ( on )  VGS (Th ) ) 2

7
Feedback Bias Circuit

IG = 0 A

VRG = 0 V

VDS = VGS

VGS = VDD – IDRD

8
Feedback Bias Q-Point
Step 1
Using values from the specification
sheet, plot the transfer curve with 4
points
Pt A(VGSTh , ID = 0 A)
Pt B (VGS(on), ID(on) )
Pt C :Assume for VGS between
VGSTh and VGS(on) and calculate ID
Pt D : Assume VGS > VGS(on) and
calculate ID
Step 2
Plot the line using
VGS = VDD – IDRD
• VGS = VDD, ID = 0 A
• ID = VDD / RD , VGS = 0 V
Step 3
The Q-point is located where the line and the transfer curve intersect
Step 4
Using the value of ID at the Q-point, solve for the other variables in the bias circuit
9
Voltage-Divider Biasing

Again plot the line and the transfer curve to find the Q-point.
Using the following equations: R2VDD
VG 
R1  R2
Input loop : VGS  VG  I D RS
Output loop: V DS  V DD  I D ( RS  R D ) 10
Voltage-Divider Bias Q-Point
Step 1
Using values from the specification sheet, plot the transfer curve
with 4 points
Pt A(VGSTh , ID = 0 A)
Pt B (VGS(on), ID(on) )
Pt C :Assume for VGS between VGSTh and VGS(on) and calculate ID
Pt D : Assume VGS > VGS(on) and calculate ID

Step 2
Plot the line using
• VGS = VG = (R2VDD) / (R1 + R2), ID = 0 A
• ID = VG/RS , VGS = 0 V

Step 3
The point where the line and the transfer curve intersect is the Q-
point.

Step 4
Using the value of ID at the Q-point,
11 solve for the other circuit
values.
Example
• Determine IDQ and VGSQ and VDS for network
below

12
p-Channel FETs

For p-channel FETs the same calculations and graphs are used,
except that the voltage polarities and current directions are reversed.

The graphs are mirror images of the n-channel graphs.

13

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