DIGITAL SWITCHING AND LOGIC DESIGN
Prof. Ananda M
Department of Electronics and Comm. Engineering
1
10/02/2020
DIGITAL SWITCHING AND LOGIC DESIGN
Unit-2 Hazards, Reliable Design Fault
Diagnosis
Prof. Ananda M
Department of Electronics and Comm. Engineering
2
10/02/2020
DIGITAL SWITCHING AND LOGIC DESIGN
Hazards, Reliable Design Fault Diagnosis
Failure tolerant design
1)Critical errors: An error occurring on one of the redundant
input’s to a specific gate is said to be critical if it causes an
incorrect gate output.
2)Sub critical errors: Occurrence at one of the redundant input’s
to a gate does not cause a fault in the gate output.
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DIGITAL SWITCHING AND LOGIC DESIGN
Hazards, Reliable Design Fault Diagnosis
Error classification in logic gates
Function Logic symbol Subcritical Critical Output as
Redundancy =3 input error a result of
Error critical
input
error
AND 0 to 1 1 to 0 1 to 0
OR 1 to 0 0 to 1 0 to 1
NAND 0 to 1 1 to 0 0 to 1
NOR 1 to 0 0 to 1 1 to 0
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DIGITAL SWITCHING AND LOGIC DESIGN
Hazards, Reliable Design Fault Diagnosis
Quadded logic:
It is a redundant logical structure which is protected against any type
of single faults and many multiple ones.
It provided with four versions of each input, and every logical circuit
appears in quadruplicate.
Fault correction is accomplished in the same circuit which performs
the logical operations by mixing the faulty signals with good ones so
that most errors are corrected within one to two levels of
propagation.
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DIGITAL SWITCHING AND LOGIC DESIGN
Quadded logic
Four identical inputs x1,x2,x3 and x4 are supplied to the
network which in turn produces four corrected outputs.
Any subcritical error at the inputs will be immediately
corrected in the first gates level.
If x1 appears to be s-a-0, then when input 1 is applied to
the circuit , the error is critical, and the outputs of both
gates 1 and 2 are incorrectly transformed from 1 to 0.
These 1 to 0 errors are subcritical for the second level of
the OR gates, the faulty signals are mixed with correct ones,
and the outputs zi are all corrected.
A failure in any OR gate which causes any of the second- Basic alternating AND-OR Quadded
level inputs to be s-a-1 may cause faults in z’s , but they will
be corrected in a third level of gates. Structure
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DIGITAL SWITCHING AND LOGIC DESIGN
Hazards, Reliable Design Fault Diagnosis
Quadded logic Basic structure:
Fig b : basic alternating NAND –NOR quadded structure
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DIGITAL SWITCHING AND LOGIC DESIGN
Symbol/ Compact notation representing quadded logic
Fig (a) Four four- input AND gate Fig (b) Four four- input OR gate Fig (c) Four one- input NOT gate
Fig (d) Four Two - input AND gate Fig (e) Four two- input AND gate
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DIGITAL SWITCHING AND LOGIC DESIGN
Symbol/ Compact notation representing quadded logic
Fig (b) Compact description for the circuit of fig(a)
Fig a: basic alternating AND –OR quadded structure
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DIGITAL SWITCHING AND LOGIC DESIGN
Symbol/ Compact notation representing quadded logic
Fig (b) Four four- input AND gate
Fig a: basic alternating NAND –NOR quadded structure
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DIGITAL SWITCHING AND LOGIC DESIGN
Quadded Logic
Fig (a). Illustration of the danger in incorrect connection procedure
Fig. (b) Correct connection procedure
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DIGITAL SWITCHING AND LOGIC DESIGN
Quadded Logic
Fig. (b) Correct connection procedure
Note: Whenever an AND gate feeds an And gate (or an OR feeds an
OR), the connection pattern at the inputs to the first and to the
second gates must be identical.
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THANK YOU
Prof. Ananda M
Department of Electronics and Comm. Engineering
[email protected]
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