Digital Signal Processors: Inderdeep Kaur Aulakh Asst. Prof. (IT), UIET Pu, CHD
Digital Signal Processors: Inderdeep Kaur Aulakh Asst. Prof. (IT), UIET Pu, CHD
10/14/20 1
INTRODUCTION
Program RAM
Data RAM
or Cache
Addr
Internal Buses
DMA
Data
Regs (A0-A15) .D1 .D2 Serial Port
Regs (B0-B15)
External .M1 .M2 Host Port
Memory
-Sync .L1 .L2 Boot Load
-Async
.S1 .S2
Timers
Control Regs
Pwr Down
CPU
Modern DSP: TI TMS320C6000
Architecture
• Very long instruction word (VLIW) size of 256 bits
– Eight 32-bit functional units with single cycle throughput
– One instruction cycle per clock cycle
• Data word size is 32 bits
– 16 (32 on C6400) 32-bit registers in each of 2 data paths
– 40 bits can be stored in adjacent even/odd registers
• Two parallel data paths
– Data unit - 32-bit address calculations (modulo, linear)
– Multiplier unit - 16 bit 16 bit with 32-bit result
– Logical unit - 40-bit (saturation) arithmetic & compares
– Shifter unit - 32-bit integer ALU and 40-bit shifter
APPLICATIONS
■ Radar and sonar
■ Communications systems
■ Process control
■ Image processing
■ Audio applications
DSP Applications Examples
Embedded system cost & input/output rates
– Low-cost, low-throughput: sound cards, 2G cell
phones, MP3 players, car audio, guitar effects
– Medium-cost, medium-throughput: printers,
disk drives, PDAs, 3G cell phones, ADSL
modems, digital cameras, video conferencing
– High-cost, high-throughput: high-end printers,
audio mixing boards, wireless basestations,
high-end video conferencing, 3-D sonar,
3-D medical reconstruction from 2-D X-rays
THANK YOU