Central Processing Unit 1 Lecture 28

Overview
 Introduction

 General Register Organization

 Stack Organization

 Instruction Formats

 Addressing Modes

 Data Transfer and Manipulation

 Program Control

 Program Interrupts

 Reduced Instruction Set Computer

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Central Processing Unit 2 Lecture 27

Program Interrupt
Types of Interrupts
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device → Data transfer request or Data transfer complete
- Timing Device → Timeout
- Power Failure

Internal interrupts (traps)

Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation

Software Interrupts
Both External and Internal Interrupts are initiated by the computer HW.
Software Interrupts are initiated by the executing an instruction.
- Supervisor Call 1. Switching from a user mode to the supervisor mode
2. Allows to execute a certain class of operations
which are
not allowed in the user mode

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Central Processing Unit 3 Lecture 27

Interrupt Procedure

Interrupt Procedure and Subroutine Call

- The interrupt is usually initiated by an internal or an external signal rather than from
the execution of an instruction (except for the software interrupt)

- The address of the interrupt service program is determined by the hardware rather
than from the address field of an instruction

- An interrupt procedure usually stores all the information necessary to define the state
of CPU rather than storing only the PC.

The state of the CPU is determined from:

 Content of the PC
 Content of all processor registers
 Content of status bits
Many ways of saving the CPU state
depending on the CPU architectures

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Central Processing Unit 4 Lecture 28

RISC- Historical BackGround

IBM System/360, 1964
• The real beginning of modern computer architecture
• Distinction between Architecture and Implementation
• Architecture: The abstract structure of a computer seen
by an assembly-language programmer

Hardware
-program
Compiler
High-Level Instruction Hardware
Language Set
Architecture
Hardware

Implementation
• Continuing growth in semiconductor memory and microprogramming
 A much richer and complicated instruction sets
 CISC(Complex Instruction Set Computer)

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Central Processing Unit 5 Lecture 28

CISC
Arguments Advanced at that time
• Richer instruction sets would simplify compilers
• Richer instruction sets would alleviate the software crisis
– move as much functions to the hardware as possible
• Richer instruction sets would improve architecture quality

CISC
• These computers with many instructions and addressing modes came to
be known as Complex Instruction Set Computers (CISC)

• One goal for CISC machines was to have a machine language instruction
to match each high-level language statement type

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Central Processing Unit 6 Lecture 28

Complex Instruction Set Computers

• Another characteristic of CISC computers is that they have instructions that

act directly on memory addresses
– For example,
ADD L1, L2, L3
that takes the contents of M[L1] adds it to the contents of M[L2] and stores the result in
location M[L3]
• An instruction like this takes three memory access cycles to execute
• That makes for a potentially very long instruction execution cycle
• The problems with CISC computers are

– The complexity of the design may slow down the processor,

– The complexity of the design may result in costly errors in the processor design and
implementation,
– Many of the instructions and addressing modes are used rarely, if ever

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Central Processing Unit 7 Lecture 28

Summary : Criticism On CISC

High Performance General Purpose Instructions

- Complex Instruction
→ Format, Length, Addressing Modes
→ Complicated instruction cycle control due to the complex decoding HW and
decoding process

- Multiple memory cycle instructions

→ Operations on memory data
→ Multiple memory accesses/instruction

- Microprogrammed control is necessity

→ Microprogram control storage takes substantial portion of CPU chip area
→ Semantic Gap is large between machine instruction and microinstruction

- General purpose instruction set includes all the features required by

individually different applications
→ When any one application is running, all the features required by the other
applications are extra burden to the application
CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT
Central Processing Unit 8 Lecture 28

RISC – Reduced Instruction Set Computers

• In the late ‘70s and early ‘80s there was a reaction to the shortcomings
of the CISC style of processors
• Reduced Instruction Set Computers (RISC) were proposed as an
alternative
• The underlying idea behind RISC processors is to simplify the instruction
set and reduce instruction execution time

• RISC processors often feature:

– Few instructions
– Few addressing modes
– Only load and store instructions access memory
– All other operations are done using on-processor registers
– Fixed length instructions
– Single cycle execution of instructions
– The control unit is hardwired, not microprogrammed

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Central Processing Unit 9 Lecture 28

RISC – Reduced Instruction Set Computers

• Since all but the load and store instructions use only registers for
operands, only a few addressing modes are needed
• By having all instructions the same length, reading them in is easy and fast
• The fetch and decode stages are simple
• The instruction and address formats are designed to be easy to decode
• Unlike the variable length CISC instructions, the opcode and register fields
of RISC instructions can be decoded simultaneously
• The control logic of a RISC processor is designed to be simple and fast
• The control logic is simple because of the small number of instructions and
the simple addressing modes
• The control logic is hardwired, rather than microprogrammed, because
hardwired control is faster

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT