Basic Logic Gates

Basic Logic Gates

NOT X Y
X Y 0 1
1 0
Y = ~X
 NOT
• Y = ~X (Verilog)
• Y = !X (ABEL)
• Y = not X (VHDL)
• Y = X’
•Y = X
•Y = X (textook)
• not(Y,X) (Verilog)
 NOT

X ~X ~~X = X

X ~X ~~X
0 1 0
1 0 1
 AND Gate
AND
X Y Z
X 0 0 0
0 1 0
Z
1 0 0
Y 1 1 1

Z = X & Y
 AND
•X & Y (Verilog and ABEL)
• X and Y (VHDL)
V
•X Y
U
•X Y
•X * Y
• XY (textbook)
• and(Z,X,Y) (Verilog)
 OR Gate
OR
X Y Z
X 0 0 0
Z 0 1 1
Y 1 0 1
1 1 1
Z = X | Y
 OR
•X | Y (Verilog)
•X # Y (ABEL)
• X or Y (VHDL)
•X + Y (textbook)
•X V Y
•X U Y
• or(Z,X,Y) (Verilog)
 Basic Logic Gates
and Basic Digital Design
• NOT, AND, and OR Gates
• NAND and NOR Gates
• DeMorgan’s Theorem
• Exclusive-OR (XOR) Gate
• Multiple-input Gates
 NAND Gate
NAND
X Y Z
X 0 0 1
0 1 1
Z
1 0 1
Y 1 1 0

Z = ~(X & Y)
nand(Z,X,Y)
 NAND Gate
NOT-AND
X Y W Z
X 0 0 0 1
W 0 1 0 1
Z
1 0 0 1
Y 1 1 1 0

W = X & Y

Z = ~W = ~(X & Y)
 NOR Gate
NOR
X Y Z
X 0 0 1
Z 0 1 0
Y 1 0 0
1 1 0
Z = ~(X | Y)
nor(Z,X,Y)
 NOR Gate
NOT-OR
X Y W Z
X 0 0 0 1
W Z 0 1 1 0
Y 1 0 1 0
1 1 1 0
W = X | Y

Z = ~W = ~(X | Y)
 Basic Logic Gates
and Basic Digital Design
• NOT, AND, and OR Gates
• NAND and NOR Gates
• DeMorgan’s Theorem
• Exclusive-OR (XOR) Gate
• Multiple-input Gates
 NAND Gate
X Z X Z
=
Y Y

Z = ~(X & Y) Z = ~X | ~Y

X Y W Z X Y ~X ~Y Z
0 0 0 1 0 0 1 1 1
0 1 0 1 0 1 1 0 1
1 0 0 1 1 0 0 1 1
1 1 1 0 1 1 0 0 0
De Morgan’s Theorem-1

~(X & Y) = ~X | ~Y
• NOT all variables
• Change & to | and | to &
• NOT the result
 NOR Gate
X X
Z Z
Y Y

Z = ~(X | Y) Z = ~X & ~Y

X Y Z X Y ~X ~Y Z
0 0 1 0 0 1 1 1
0 1 0 0 1 1 0 0
1 0 0 1 0 0 1 0
1 1 0 1 1 0 0 0
De Morgan’s Theorem-2

~(X | Y) = ~X & ~Y
• NOT all variables
• Change & to | and | to &
• NOT the result
 De Morgan’s Theorem
• NOT all variables
• Change & to | and | to &
• NOT the result
• --------------------------------------------
• ~X | ~Y = ~(~~X & ~~Y) = ~(X & Y)
• ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y
• ~X & !Y = ~(~~X | ~~Y) = ~(X | Y)
• ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y
 Basic Logic Gates
and Basic Digital Design
• NOT, AND, and OR Gates
• NAND and NOR Gates
• DeMorgan’s Theorem
• Exclusive-OR (XOR) Gate
• Multiple-input Gates
 Exclusive-OR Gate

XOR
X Y Z
X
Z 0 0 0
Y
0 1 1
Z = X ^ Y 1 0 1
xor(Z,X,Y)
1 1 0
 XOR
•X ^ Y (Verilog)
•X $ Y (ABEL)
•X @ Y
X  Y (textbook)
• xor(Z,X,Y) (Verilog)
 Exclusive-NOR Gate

XNOR
X Y Z
X
Z 0 0 1
Y
0 1 0
Z = ~(X ^ Y) 1 0 0
Z = X ~^ Y 1 1 1
xnor(Z,X,Y)
 XNOR
• X ~^ Y (Verilog)
• !(X $ Y) (ABEL)
•X @ Y
X  Y
• xnor(Z,X,Y) (Verilog)
 Basic Logic Gates
and Basic Digital Design
• NOT, AND, and OR Gates
• NAND and NOR Gates
• DeMorgan’s Theorem
• Exclusive-OR (XOR) Gate
• Multiple-input Gates
Multiple-input Gates

Z1 Z2

Z3 Z4
 Multiple-input AND Gate

Z1

Output Z 1 is HIGH only if all inputs are HIGH

An open input will float HIGH

Z2

Output Z 2 is LOW only if all inputs are LOW

Z3

Output Z 3 is LOW only if all inputs are HIGH

Z4

Output Z 4 is HIGH only if all inputs are LOW