0% found this document useful (0 votes)
84 views52 pages

Thumb Instruction

The document summarizes the Thumb instruction set used by ARM7TDMI processors. It describes how Thumb instructions are 16-bit and operate in Thumb state, while ARM instructions are 32-bit and operate in ARM state. Processors can switch between ARM and Thumb states using specific instructions. Thumb instructions have fewer capabilities than ARM but allow for higher code density. The document provides details on Thumb instruction encoding, data processing instructions, branching, and exception handling.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
84 views52 pages

Thumb Instruction

The document summarizes the Thumb instruction set used by ARM7TDMI processors. It describes how Thumb instructions are 16-bit and operate in Thumb state, while ARM instructions are 32-bit and operate in ARM state. Processors can switch between ARM and Thumb states using specific instructions. Thumb instructions have fewer capabilities than ARM but allow for higher code density. The document provides details on Thumb instruction encoding, data processing instructions, branching, and exception handling.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 52

THUMB INSTRUCTION SET

1 of 37
Objectives

• To understand 16-bit Thumb state operation of ARM Processor.


• To understand the features of Thumb state operation and how
Thumb instructions decompress to ARM Mode.
• To know the technique of switching between ARM and Thumb
mode of operations.
• To know the similarities and differences between ARM and
Thumb mode of operation
• To understand exception handling and branching in Thumb
mode.
• To understand operation of data processing instructions and data
transfer instructions in Thumb mode.

2 of 37
CPU Instruction Set

ARM7TDMI processor has two instruction sets:


• the standard 32-bit ARM instruction set
• a 16-bit THUMB instruction set.

3 of 37
Processor Operating States

ARM state
which executes 32-bit, word-aligned ARM instructions.

THUMB state
which operates with 16-bit, halfword-aligned THUMB
instructions.

4 of 37
Thumb Instruction Set

• ARM architecture versions v4T and above define a 16-bit


instruction set called the Thumb instruction set. The
functionality of the Thumb instruction set is a subset of the
functionality of the 32-bit ARM instruction set.
• A processor that is executing Thumb instructions is operating
in Thumb state. A processor that is executing ARM instructions
is operating in ARM state.

5 of 37
Thumb Instruction Set

• A processor in ARM state cannot execute Thumb instructions,


and a processor in Thumb state cannot execute ARM
instructions. You must ensure that the processor never receives
instructions of the wrong instruction set for the current state.
• Each instruction set includes instructions to change processor
state.

Note: ARM processors always start executing code in ARM state.

6 of 37
7 of 37
8 of 37
9 of 37
Thumb state entry

10 of 37
11 of 37
12 of 37
BX and BLX

13 of 37
Eg

14 of 37
*  CODE32 instructs the assembler to interpret subsequent
instructions as ARM instructions
* CODE16 instructs the assembler to interpret subsequent
instructions as THUMB instructions

15 of 37
Example

16 of 37
17 of 37
Binary Encoding

18 of 37
19 of 37
20 of 37
Thumb Programming Model

21 of 37
22 of 37
23 of 37
24 of 37
25 of 37
26 of 37
27 of 37
28 of 37
29 of 37
30 of 37
31 of 37
Conti.
* All the data processing instructions that operate with and on the 'Lo'
registers update the condition code bits (the S bit is set in the
equivalent ARM instruction).
* The instructions that operate with and on the 'Hi' registers do not
change the condition code bits, with the exception of CMP which only
changes the condition codes.
* The instructions that are requiring '1 or 2 Hi regs' must have one or
both register operands specified in the 'Hi' register area.
* 3, 7 and 8-bit immediate fields is possible depending upon the
instructions.
* Shift amount for shifting instruction is 5 bit.

32 of 37
33 of 37
34 of 37
35 of 37
36 of 37
* The following instructions perform ALU operations on to Lo
register pair.
* All instructions in this group set the CPSR condition codes.

37 of 37
Instructions with high register range
only cmp sets CC

38 of 37
39 of 37
40 of 37
41 of 37
42 of 37
43 of 37
44 of 37
45 of 37
46 of 37
Conditional Branch

47 of 37
48 of 37
49 of 37
Egs

50 of 37
51 of 37
52 of 37

You might also like