Teaching Digital Logic courses with
Altera Technology
Tutorial #1
Outline
Learn how to use Quartus:
- Creating projects in Quartus
- Targeting a project for a DE1-SoC Board
- Downloading a circuit onto a DE1-SoC board
- Compiling and debugging
Overview of tutorials and lab exercises for teaching digital
logic using Quartus
2
Exercise 1: A Simple Quartus Project
Open a Quartus Project
Compile a simple circuit
- 10-bit shift register
- Register input: switch
- Shift on key press
- Register values displayed on LEDs
Program FPGA with circuit
Examine behavior on the board
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Step 1: Start Quartus II
Project Navigator
Status Window
Message Window
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Step 2: Create a New Project
Click File Menu
Select New Project Wizard
This will open a new window where project information can
be specified
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Project Name and Directory
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Create an Empty Project
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Add Source Files to Project
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Specify FPGA Device
Select the FPGA device on the board
- Cyclone V Family – 5CSEMA5F31C6
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Additional EDA Tools
Specify Tools, in addition to Quartus II, that you will use
These are unnecessary for small student designs
- Leave all entries as <None>
- Press Next
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New Project Summary
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Simple Project
SW[0] Input
KEY[0] Reset_N 10-bit Shift Register
KEY[1] Clock
LED[9] … LED[2] LED[1] LED[0]
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Step 3: Open Source File
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Step 4: Assign Pins to connect switches/lights to
inputs and outputs of your circuit
Click Assignments, then Import Assignments…
Import file
- DE1_SoC.qsf
Imports locations for predefined port names, such as SW,
LED, KEY, and others
- Can be done manually too
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Step 5: Compile Design
// Begin: Write Control
always @ (posedge wrbusy_i nt)
begin
// Begin:
write0 Write C ontrol
<= 1'b1;
always <=
write1 @ (p osedge wrbusy_int)
1'b0;
begin <= 1'b0;
writex
// Begi
write0n: Write Control
<= 1'b1;
end a lways <=@ (posedge wrbusy_int)
write1 1'b0;
b egin <= 1'b0;
writex
always @ (negedge
write0wrbusy_i nt)
<= 1'b1;
beginend write1 <= 1'b0;
write0 <= writex
1'b0; <= 1'b0;
end always @ (n egedge wrbusy_int)
begine nd
write0 <= 1'b0;
always @ (posedge write0_d one )
end a lways @ (negedge wrbusy_int)
Verilog,
begin b egin
write1 <= write0
1'b1; <= 1'b0;
always @ (p osedge write0_done)
begine nd
write1 <= 1'b1;
a lways @ (posedge write0_done)
b egin
VHDL
write1 <= 1'b1;
Placement Timing &
Synthesis & Routing Power
Analysis
Assembler Report
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Step 6: Examine Compilation Report
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Step 7: Program the Board
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Step 8: See your design work on the board
Press the KEY[0] to clock the circuit
SW[0] is the input to the shift register
Reset the shift register using KEY[1]
SW[0] Input
KEY[1] Reset_N 10-bit Shift Register
KEY[0] Clock
Red LEDs
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Hands-On Session
Please read the instructions at
- “/exercise1/simple_instructions.pdf”
Use provided source code “simple.v”
We will be walking around to help with any issues (such as
USB programming)
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Next Exercise
Go into the /exercise2 subfolder
Open the stopper.qpf Quartus II project
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Exercise 2: Stopper
Shift the contents of a register once every ~0.1 second
- The circuit is clocked using a 50MHz clock
Press KEY[0] to start or stop the shift register
- FSM examines if the key was pressed
Purpose:
- Look at FSM implementation in Quartus II
- Finite State Machine Viewer
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Circuit Diagram
KEY[0]
FSM
Clock
Fast Slow enable
Divider 10-bit Shift Register
Clock Clock
Red LEDs
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Step 1: Open Stopper Project
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Step 2: Compile and Program
Compile the design
Program the design onto the board
How does it work?
- Press KEY[0] to start/stop the circuit
- Press KEY[1] to reset the circuit
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Step 3: Examine the FSM Source Code
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Step 4: FSM Viewer
Open the FSM
Viewer
- Click Tools
- Expand Netlist
Viewers
- Click State
Machine Viewer
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Examine State Machine
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Hands-On Session
Please read the instructions at
- “/exercise2/stopper_instructions.pdf”
Use provided project “stopper.qpf”
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Exercise 3: Signal Tap II Logic Analyzer
Go into /exercise3 subfolder
Open the signaltap.qpf Quartus II project
Compile the project, and program the board
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SignalTap II Embedded Logic Analyzer
A logic analyzer IP core
- Instantiate in your Verilog code
Connects to the board on which a design is running
Collects data when a trigger event occurs
Displays data on your computer
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SignalTap II Operation
USB-Blaster
cable
KEY[0] SignalTap Module
KEY[1] FSM
enable
10-bit Shift Register
Clock Clock
FPGA
Red LEDs
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Setup SignalTap II
Specify cable
connection
Specify Clock
signal
Specify signals
to display
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Recompile Project
For changes to take effect recompile project
Once recompiled, download it to the board
Note: The circuit will be larger than before
- Memory is used to store captured data
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Setup Event Trigger
Click here to
begin capture
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Trigger the event and Analyze the results
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Hands-On Session
Please read the instructions at
- “/exercise3/signtaltap_instructions.pdf”
Use provided project “signaltap.qpf”
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Summary of Tutorial #1
Learned how to
- Use Quartus II CAD Software
- Compile projects in Quartus II
- Target design onto DE1-SoC
- View results of compilation
- Use SignalTap II
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Tutorials
Introduction to Quartus II
Tutorials
- Getting Started with Altera’s DE-series Lab Boards
- Introduction to Quartus
With Verilog, or VHDL
- Using library modules (LPMs)
With Verilog or VHDL
- Quartus Simulation
- Using ModelSim for Altera
- Using TimeQuest Timing Analyzer
- Signal Tap II Logic Analyzer
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Digital Logic Lab Exercises
Lab exercises
- Verilog and VHDL versions
- From basic logic gates to simple processors:
1. Switches, Lights, and Multiplexers
2. Numbers and Displays
3. Latches, Flip-flops, and Registers
4. Counters Sample curriculum
5. Real-time Clock and Timers
6. Adders, Subtractors, and Multipliers
7. Finite State Machines
8. Memory Blocks
9. A Simple Processor
10. An Enhanced Processor
11. Algorithms in Hardware
12. Digital Signal Processing
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Lab Exercises and Solutions
Exercises and complete solutions on U.P. web site
- Password protected (Professors/Lecturers)
- Includes all Quartus II projects
- Includes all figures and source text
(allows Instructors to add their own material)
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Organization of Lab Exercises
Simple HDL assignments that directly correspond to
Boolean equations
- No magic!
Block-based design in which each block of code
corresponds to a well-defined subcircuit
- HDL code is not a “program”!!
Smaller circuits are built first, and then used to
construct larger ones
- Good design practice
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Lab 1: Switches and Lights
/* connect switches to lights through FPGA */
assign light_0 = switch_0;
lab1_part1.v
Part 1 assign light_1 = switch_1;
... Suggested
solution
/* build a 2-to-1 multiplexer */
Part 2
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… Lab 1
assign m = (~s & x) | (s & y);
lab1_part2.v
Part 2 …
Make 8 copies, connect to 8 red LEDs Suggested
solution
Part 3
Build a more complex multiplexer:
3-bit wide 5-to-1 multiplexer
lab1_part3.v
Suggested
solution
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… Lab 1
lab1_part4.v
Part 4
Suggested
solution
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… Lab 1
Part 5 Make 5 copies of this
Part 5
lab1_part5.v
Suggested
solution
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Lab 2 and Lab 3
Numbers and Displays
- Display binary numbers on 7-segment displays
- Convert binary to Binary Coded Decimal
- Simple ripple-carry addition
Latches and Flip-flops
- Implement RS latch in an FPGA
- Implement D latch
- Master-slave flip-flop as latches
- D registers as Verilog code
always @(posedge Clock or negedge Resetn)
Q <= R;
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Lab 4: Counters
lab4_part1.v
Suggested
solution
Part 1
assign Enable_0 = SW[1];
ToggleFF (Enable_0, Clock, Clear, Count_0);
assign Enable_1 = Count_0 & Enable_0;
ToggleFF (Enable_1, Clock, Clear, Count_1);
...
… Lab 4
/* use some more advanced Verilog */
Part 2
… lab4_part2.v
Count <= Count + 1; Suggested
...
solution
Count
Part 5
part6.v
Cou
Suggested
nt
solution
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To Students: Write “Obvious” HDL Code
Comparator
assign T = A + B; Adder
always @ (T)
if (T > 9)
begin
Z = 6; C = 1;
end
else
Multiplexer that selects
begin constants
Z = 0; C = 0;
end
assign S = T + Z;
Adder
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