Cortex M3

Introduction
• ARM was formed in 1990 as Advanced RISC Machines.
• In 1991, ARM introduced the ARM6 processor family
• ARMv4T architecture- ARM7TDMI (Thumb)
• ARMv5E architecture – ARM9 ARM926E-S ARM946E-S
• ARMv6 architecture - ARM1136J(F)-S, ARM1156T2(F)-S
• ARMv7 – ARM M,
ARM R ARM7TDMI processor
T -Thumb instruction support,
ARM A
E – Enhanced (DSP applications) D -JTAG debugging,
MMUs -“26” or “36,” M -fast multiplier,
MPUs-“46” Synthesizable – S I -an embedded ICE module.

Jazelle technology - J
A Profile :
• Application processors - high-end embedded OS(e.g.,
Symbian, Linux, and Windows Embedded).
• highest processing power
• virtual memory system (MMU)
• enhanced Java support
• Example products -high-end mobile phones

R Profile :
• Real-time, high-performance
• high processing power
• high reliability
• lowlatency is important.
 M Profile :
• low-cost applications
• processing efficiency
• cost, power consumption, low interrupt latency,
• ease of use
• as industrial control applications

Cortex- M3 processor is based on one profile of the v7

architecture, called ARM v7-M
• The ARMv7-M architecture contains the following key areas:
• Programmer’s model
• Instruction set
• Memory model
• Debug architecture
Instruction Set Development
Two different instruction sets are supported
on the ARM processor:
– ARM instructions -32 bits
dynamically switched
– Thumb instructions -16 bits.
In 2003 - Thumb-2 instruction
• superset of Thumb instructions
• 16-bit and 32-bit instructions.
Applications of Cortex M3
• Low-cost microcontrollers
• Automotive
• Data communications
• Industrial control
• Consumer products
Cortex M3 – basics
• 32-bit microprocessor.
• 32-bit data path
• 32-bit register bank
• 32-bit memory interfaces
• Harvard architecture
• Unified memory system
• Optional Memory Protection Unit
• Supports both little endian and big endian
• number of fixed internal debugging components
• Program status register
– Application Program Status register (APSR)
– Interrupt Program Status register (IPSR)
– Execution Program Status register (EPSR)
Special function registers:
• Program Status registers (PSRs)
• Interrupt Mask registers (PRIMASK, FAULTMASK, and BASEPRI)
• Control register (CONTROL)
• Operation modes

thread mode,
privileged access rights.

exception takes place,

• switch to a privileged state
• can switch back by changing control
reg. bit

• can switch to user access level using

the control register
• control register bit 0 is 1 -processor mode and
access level change when an exception takes
place.
• control register bit 0 is 0 - processor mode
changes when an exception takes place
The Built -In Nested Vectored Interrupt Controller
• Nested interrupt support
• Vectored interrupt support
• Dynamic priority changes support
• Reduction of interrupt latency
• Interrupt masking
Nested Interrupt Support
• external interrupts
• system exceptions
Vectored Interrupt Support
• Starting address of the interrupt service routine (ISR) is
located from a vector table in memory
Dynamic Priority Changes Support
– Priority levels of interrupts can be changed by software
during run time.
Reduction of Interrupt Latency
• automatic saving and restoring some register contents
• reducing delay in switching from one ISR to another
• handling of late arrival interrupts.
Interrupt Masking
• BASEPRI,
• PRIMASK,
• FAULTMASK
The Memory Map
• 4 GB memory space can be divided into ranges
INSTRUCTION SET
• The Cortex-M3 supports the Thumb-2 instruction set.
• No state switching overhead, saving both execution time and instruction
space
• No need to separate ARM code and Thumb code source files, making
software development and maintenance easier
• Efficiency and performance, in turn making it easier to write software,
• Best code density/performance
Interrupts and Exceptions
• System exceptions
• external Interrupt Request
• interrupt priority handling and nested interrupt support
(nested interrupts)
• .
Debugging Support
• Cortex-M3 includes a number of debugging features.
• program execution controls - Debug Access Port- SWJTAG
Embedded Trace Macrocell-Trace Port Interface Unit
• halting and stepping
• instruction breakpoints -
• data watch points, registers and memory accesses
• Data Watch point and Trace unit
• profiling, and traces
 Instruction Set
Assembly Basics:
• Instruction format:
Label opcode operand1, operand2, ...; Comments
– first operand is the destination of the operation
– No of operands depend on instruction
• define constants using EQU
– NVIC_IRQ_SETEN0 EQU 0xE000E100
– NVIC_IRQ0_ENABLE EQU 0x1
– LDR R0,=NVIC_IRQ_SETEN0; ; LDR here is a pseudo-instruction
– MOV R1,#NVIC_IRQ0_ENABLE ; Move immediate data to register
– STR R1,[R0]
• DCI (Define Constant Instruction) -used to code an instruction.
– Ex: DCI 0xBE00 ; Breakpoint (BKPT 0)
• DCB (Define Constant Byte) for byte size constant values
• Ex: HELLO_TXT DCB "Hello\n",0
• DCD (Define Constant Data) for word size constant values
• Ex: MY_NUMBER DCD 0x12345678
 Instruction Descriptions
Moving Data
• Data transfers can be of one of the following types:
– Moving data between register and register Ex: MOV R2,R8
– Moving data between memory and register ex : LD,ST
– Moving data between special register and register ex: MRS R0, PSR
– Moving an immediate data value into a register ex: MOVS R0, #0x12
• Load and Store. Load (LDR), STR
• The transfers can be in different data sizes (byte, half word, word, double
word),
• Multiple Load and Store operations can be combined into
single instructions called LDM and STM
• exclamation mark (!) in the instruction specifies whether the
register Rd should be updated after the instruction is
completed.
• memory accesses with preindexing and postindexing.
– Pre indexing LDR.W R0,[R1, #offset]! ;
– Post indexing LDR.W R0,[R1], #offset ;
• other types of memory operation are stack PUSH and
stack POP.
– PUSH {R0, R4-R7, R9} ; Push R0, R4, R5, R6, R7, R9 into ; stack memory
– POP {R2,R3} ; Pop R2 and R3 from stack
• LDR and ADR pseudo-instructions used to set
registers to a program address value.
– LDR R0, =address1 assembler will automatically set the LSB to 1
– ADR R0, address1
• Branch Instruction:
– B label ; Branch to a labeled address
– BX reg ; Branch to an address specified by a register
– BL label ; Branch to a labeled address and save return
address in LR
– BLX reg ; Branch to an address specified by a register and
save return ; address in LR.
– MOV R15, R0 ; Branch to an address inside R0
– LDR R15, [R0] ; Branch to an address in memory location
; specified by R0
• MOVGT R2, R0 ; R2 = R0
• MOVGT R3, R1 ; R3 = R1
• MOVLE R2, R0 ; Else R2 = R1
• MOVLE R3, R1 ; R3 = R0
• CMP R0, R1 ; Calculate R0 – R1 and update flag
• CMP R0, #0x12 ; Calculate R0 – 0x12 and update flag
• CMN R0, R1 ; Calculate R0 – (-R1) and update flag
• CMN R0, #0x12 ; Calculate R0 – (-0x12) and update flag
• CBZ R0,loop1exit ; if loop counter = 0 then exit the loop
• TST R0, R1 ; Calculate R0 AND R1 and update flag
• TST R0, #0x12 ; Calculate R0 AND 0x12 and update flag