CHANDIGARH UNIVERSITY

University Institute of Engineering

Department of Electronics & Communication Engineering

FINITE STATE MACHINES (FSMs)

Prepared By:
Rajpreet Singh
 Finite State Machine
• A generic model for sequential circuits used in
sequential circuit design

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 Finite state machine block diagram
PREVIOUS STATE

STATE MEMORY
SET
D Q
OUTPUTS
NEXT CLR Q
NEXT STATE STATE OUTPUT LOGIC
INPUTS

...
LOGIC
SET
D Q

CLR Q

CLK

• State memory: Set of n flip-flops that hold the state of the machine
(up to 2^n distinct states)
• Next state logic: Combinational circuit that determines the next
state as a function of the current state and the input
• Output logic: Combinational circuit that determines the output as a
function of the current state and the input
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 Finite State Machine types
PREVIOUS STATE

STATE MEMORY
SET
D Q
OUTPUTS

• Mealy machine: The INPUTS

COMBINATIONAL
NEXT
STATE
CLR Q
OUTPUT LOGIC

...
LOGIC
SET
D Q

output depends on the CLR Q

current state and input CLK

PREVIOUS STATE

• Moore machine: The STATE MEMORY

D
SET
Q
OUTPUTS

output depends only on INPUTS

COMBINATIONAL
NEXT
STATE
CLR Q
OUTPUT LOGIC

...
LOGIC
SET
D Q

the current state CLR Q

– State = output state CLK

PREVIOUS STATE
machine: A Moore type STATE MEMORY

FSM where the current NEXT

D
SET

CLR
Q

Q OUTPUTS
COMBINATIONAL

state is the output INPUTS STATE

...
LOGIC
SET
D Q

CLR Q

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CLK
 State diagram

A state diagram represents the states as circles and the

transitions between them as arrows annotated with inputs and
outputs
1/0
0/0
0/1
00 10

0/1
1/0 0/1 1/0

1/0
01 11
 

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 Analysis of FSMs with D flip-flops
• Determine the next state and output functions
• Use the functions to create a state/output table
that specifies every possible next state and
output for any combination of current state and
input

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EXAMPLE
X
SET
D Q A

CLR Q A’

SET
D Q B

CLR Q B’
CP

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 Next state equations and state table
A B x A+ B+ y
• A+=Ax+Bx 0 0 0 0 0 0
• B+=A΄x 0 0 1 0 1 0
• Y=(A+B)x΄ 0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

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 • A+=Ax+Bx
• B+=A΄x
• Y=(A+B)x΄
X
D
SET
Q A A B x A+ B+ y

CLR Q A’
0 0 0
0 0 1
0 1 0
SET
0 1 1
D Q B

1 0 0
CLR Q B’
CP 1 0 1

Y
1 1 0
1 1 1

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Sequential circuit design methodology
• From the description of the functionality or the
state/timing diagram find the state table
• Encode the states if the state table contains letters
• Find the necessary number of flip-flops
• Select flip/flop type
• From the state table, find the excitation tables and
output tables
• Using Karnaugh maps find the flip-flop input logic
expressions
• Draw the circuit logic diagram

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Example: Design the sequential circuit of the
following state diagram
0

00
1

0
1
01 11
1

0
10

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 State/excitation table
A B x A+ B+ DA DB JA KA JB KB

               
0 0 0
               
0 0 1
               
0 1 0
               
0 1 1
               
1 0 0
               
1 0 1
               
1 1 0
               
1 1 1

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Karnaugh maps for combinational circuit

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Circuit logic diagram

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Example: counter
000

001 110

010 101

100

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 Self-correcting state machines
• The previous example did not include two possible
states “011” and “111”. If the counter unexpectedly
falls into one of those states there are two possibilities:
– The counter will recover by entering a valid state after a finite
number of cycles (self-correcting)
– The counter will stay in a non-valid state until the f/fs are
reset (not self-correcting)
• Finite state machines should be designed to be self
correcting by assigning non-valid states to a valid next
state (no don’t cares in the excitation table)

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 Example
• Design a self-correcting one-digit BCD counter

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 Example
• Design the circuit for the left and right indicator lights
in a car.
• Inputs:
– Clock: Frequency equal to the flashing rate
– Reset: for initializing flip-flops
– Left, Right: normally zero, remain one for the duration of the
turn
– Emergency: Rising edge active, both lights should be flashing

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