VHDL Design Units

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 VHDL Design Units
• Entity • Primary Design Units
• Package
• Configuration

• Architecture • Secondary Design units

• Package body

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 VHDL Terms
• Entity :

All designs are expressed in terms of entities. An

entity is the most basic building block in a design.
If the design is hierarchical, then the top-level
description will have lower-level descriptions
contained in it. These lower-level descriptions will
be lower-level entities contained in the top-level
entity description

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 VHDL Terms
• Architecture :

All entities that can be simulated have an

architecture description. The architecture describes
the behaviour of the entity. A single entity can
have multiple architectures. One architecture might
be behavioural while another might be structural
description of the design.

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 VHDL Terms
• Configuration :

A Configuration statement is used to bind a

component instance to an entity-architecture pair.

• Package :

A package is a collection of commonly used data

types and subprograms in a design. (like a toolbox
that contains tools used to build designs)
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 An Entity and its Model

Entity
Entity Declaration
Hardware Model
Abstraction
of a
Digital System

Architecture Bodies

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 Components

Package Entity
Declaration (Interface)

Architecture
(Function)
Package
Body
Configuration

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 A VHDL File

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 Design Entity

E n t it y
E n t it y D e c la r a t io n
I n t e r fa c e D e c la r a t io n

A r c h it e c t u r e B o d y

F u n c t io n a l D e fin it io n

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 Entity
• Declares the design name.
• Provides the port information
– Describes the interface of the design entity.
• The interface includes all inputs, outputs and bi-directional
signals and generics.
• A declarative part to declare Subprograms, types and
constants .
– Declarations are visible to all the architectures assigned
to the entity
– An entity may contain its own passive statements.

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 Entity Syntax
Entity entity-name is
[generic (list-of-generics-and-their-types);]

[port (list-of-interface-port-names-and-their-types);]

[entity-item-declarations]
[begin
entity-statements]

End [entity][entity_name];

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 PORTS
• Each I/O signal in an entity declaration is a port.

• Must have a name, a direction (mode) and a data type.

• A port is a data object (signal).

• It can be assigned values and used in expressions.

• port (

portname : [mode] subtype_indication [:= init_value]

{; portname : [mode] subtype_indication [:= init_value]}

);

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 Port Data Types
• Pre defined
– Boolean
– bit
– bit_vector
– integer
• IEEE std_logic_1164
– std_ulogic , std_logic
– std_logic_vectors

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 Modes

• In - input port, read only

• out - output port , write only

• inout - bi-directional port, read/write,

multiple drivers

• buffer - read and update, single driver

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 VHDL Entity
• entity- name of a function and its
interfaces

a_in
sum_out
b_in Full adder

cy_ in cy_out

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 Entity
entity fulladder is

port ( a_in,b_in,cy_in : in bit ;

sum_out,cy_out : out bit ) ;

end fulladder ;

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 Entity Declarations

a 4 4 Sum
b 4
add4
ci co

Entity add4

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 Entity Declaration
Example
Entity add4 is
port
(a : in std_logic_vector(3
std_logic_vector downto 0);
b : in std_logic_vector(3
std_logic_vector downto 0);
ci : in std_logic;
std_logic
sum : out std_logic_vector(3
std_logic_vector downto 0);
co : out std_logic);
std_logic
end add4;

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 Example

entity and 2 is --and gate

port (a,b : in bit; a
y
y : out bit); b
end and2;
architecture dataflow of and2 is
Begin
y<=a and b;
end dataflow;

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