BITS Pilani
Pilani Campus
DIGITAL systems (Combinational circuit)
RKTiwary
Mano
Chapter 4:
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Karnaugh Map with don’t care
Ex.3-9 Simplify the F (w, x, y, z)= ∑(1, 3, 7, 11, 15) with
don’t-care conditions d(w, x, y, z) = ∑(0, 2, 5)
In part (a) with minterms 0 and 2 F = yz + w’x’
In part (b) with minterm 5 F = yz + w’z
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Example don’t care
F (w, x, y, z)= ∑ m(2, 4, 7, 8, 9,11,15) + d(1,6, 12, 13)
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Combinational Circuits
Output is function of input only
i.e. no feedback
Combinational
n inputs •
•
•
•
m outputs
• Circuits •
When input changes, output may change (after a delay)
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Analysis
▪ Given a circuit, find out its function A
?
B
F1
▪ Function may be expressed as:
C
A
B
C
A
B
– Boolean function ?
A
F2
C
B
C
– Truth table
Design
▪ Given a desired function, determine its circuit
▪ Function may be expressed as:
– Boolean function
– Truth table
?
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
• Analysis Procedure
• Boolean Expression Approach
A
B
F1
C ABC
A A+B+C
B AB'C'+A'BC'+A'B'C
C
A
B (A’+B’)(A’+C’)(B’+C’)
A
F2
C
AB+AC+BC
B
C F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Analysis Procedure
Truth Table Approach
A B C F 1 F2
A= 0 0 0 0 0 0
B= 0 0 0
F1
C= 0
A= 0 0
B= 0 0
C= 0
0 1
A= 0
B= 0
0
A= 0 0
F2
C= 0
0
B= 0
C= 0
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Analysis procedure
Truth Table Approach A B C F 1 F2
A= 0 0 0 0 0 0
B= 0 0 1
F1 0 0 1 1 0
C= 1
A= 0 1
B= 0 1
C= 1
0 1
A= 0
B= 0
0
A= 0 0
F2
C= 1
0
B= 0
C= 1
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Analysis Procedure
Truth Table Approach A B C F1 F 2
A= 0 0 0 0 0 0
B= 1 0 1
F1 0 0 1 1 0
C= 0
A= 0
0 1 0 1 0
1
B= 1 1
C= 0
0 1
A= 0
B= 1
0
A= 0 0
F2
C= 0
0
B= 1
C= 0
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Analysis Procedure
Truth Table Approach A B C F 1 F2
A= 0 0 0 0 0 0
B= 1 0 0
F1 0 0 1 1 0
C= 1
A= 0
0 1 0 1 0
1
B= 1 0 0 1 1 0 1
C= 1
0 0
A= 0
B= 1
0
A= 0 1
F2
C= 1
1
B= 1
C= 1
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Analysis Procedure
Truth Table Approach A B C F 1 F2
A= 1 0 0 0 0 0
B= 0 0 1
F1 0 0 1 1 0
C= 0
A= 1
0 1 0 1 0
1
B= 0 1 0 1 1 0 1
C= 0 1 0 0 1 0
0 1
A= 1
B= 0
0
A= 1 0
F2
C= 0
0
B= 0
C= 0
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Analysis Procedure
Truth Table Approach A B C F 1 F2
A= 1 0 0 0 0 0
B= 0 0 0
F1 0 0 1 1 0
C= 1
A= 1
0 1 0 1 0
1
B= 0 0 0 1 1 0 1
C= 1 1 0 0 1 0
0 0
A= 1 1 0 1 0 1
B= 0
1
A= 1 1
F2
C= 1
0
B= 0
C= 1
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Analysis Procedure
Truth Table Approach
A B C F 1 F2
A= 1 0 0 0 0 0
B= 1 0 0
F1 0 0 1 1 0
C= 0
A= 1
0 1 0 1 0
1
B= 1 0 0 1 1 0 1
C= 0 1 0 0 1 0
1 0
A= 1 1 0 1 0 1
B= 1
0 1 1 0 0 1
A= 1 1
F2
C= 0
0
B= 1
C= 0
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Analysis Procedure
Truth Table Approach
A B C F 1 F2
A= 1 0 0 0 0 0
B= 1 1 1
F1 0 0 1 1 0
C= 1
A= 1
0 1 0 1 0
1
B= 1 0 0 1 1 0 1
C= 1 1 0 0 1 0
1 0
A= 1 1 0 1 0 1
B= 1
1 1 1 0 0 1
A= 1 1
C= 1
F2 1 1 1 1 1
1
B= 1
C= 1 B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C
F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Binary Adder
Half Adder
▪ Adds 1-bit plus 1-bit x S
▪ Produces Sum and Carry y
HA
C
x
+ y
x y ───
C S
C S
0 0 0 0
0 1 0 1
x S
1 0 0 1
1 1 1 0
C
y
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Binary Adder
Full Adder
▪ Adds 1-bit plus 1-bit plus 1-bit x S
y FA
▪ Produces Sum and Carry z C
x
+ y
y + z
x y z C S
0 0 0 0 0 0 1 0 1
───
0 0 1 0 1 x 1 0 1 0 C S
0 1 0 0 1 z
S = xy'z'+x'yz'+x'y'z+xyz = x y z
0 1 1 1 0
y
1 0 0 0 1
1 0 1 1 0 0 0 1 0
1 1 0 1 0 x 0 1 1 1
1 1 1 1 1 z
C = xy + xz + yz
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Binary Adder
Full Adder
S = xy'z'+x'yz'+x'y'z+xyz = x y z
x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C
z
z
y
z
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Binary Adder
Full Adder
x S
y HA HA
z C
x’y+xy’
x x’yz’+xy’z’+x’y’z+xyz
S
xy (x’y+y’x)z
y
C
x’yz+xy’z+xy
z
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Binary Adder
x3x2x1x0 y3y2y1y0
c3 c2 c1 .
+ x3 x2 x1 x0
Carry
Cy Binary Adder C0 + y3 y2 y1 y0
Propagate
Addition ────────
Cy S3 S2 S1 S0
S3S2S1S0
x3 x2 x1 x0
y3 y2 y1 y0
0
FA FA FA FA
C4 C3 C2 C1
S3 S2 S1 S0
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Binary Adder
Carry Propagate Adder
x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
CPA
Cy C0 CPA
Cy C0 0
S3 S2 S1 S0 S3 S2 S1 S0
S7 S6 S5 S4 S3 S2 S1 S0
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Design Procedure
Given a problem statement:
▪ Determine the number of inputs and outputs
▪ Derive the truth table
▪ Simplify the Boolean expression for each output
▪ Produce the required circuit
Example:
Design a circuit to convert a “BCD” code to “Excess 3”
code
4-bits 4-bits
0-9
?
values Value+3
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Design Procedure
BCD-to-Excess 3 Converter
00 01
C
11 10
C
A B C D w x y z
00
0 0 0 0 0 0 1 1 1 1 1
0 0 0 1 0 1 0 0 01 1 1 1 1
11 x x x x B x x x x B
0 0 1 0 0 1 0 1 A 1 1 x x
A 1 x x
0 0 1 1 0 1 1 0 10
D D
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1
1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x B x x x x B
A 1 x x A 1 x x
1 0 1 1 x x x x
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Design Procedure
BCD-to-Excess 3 Converter
A B C D w x y z
0 0 0 0 0 0 1 1 A
w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 x
B
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0 C y
1 0 1 0 x x x x
1 0 1 1 x x x x D z
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 1 x x x x x = B’(C+D) + B(C+D)’ z = D’
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Design Process Seven-Segment Decoder
a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
d g
0 0 1 0 1101101 y ? e
0 0 1 1 1111001 f
z g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx 1 1 1
x x x x x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
d=... c=...
1 1 1 1 xxxxxxx
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BCD Adder
+ x3 x2 x1 x0
4-bits plus 4-bits
Operands and Result: 0 to 9 + y3 y2 y1 y0
────────
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0
Cy S3 S2 S1 S0
0+0 0 0 0 0 0 0 0 0 =0 0 0 0 0 0
0+1 0 0 0 0 0 0 0 1 =1 0 0 0 0 1
0+2 0 0 0 0 0 0 1 0 =2 0 0 0 1 0
0+9 0 0 0 0 1 0 0 1 =9 0 1 0 0 1
1+0 0 0 0 1 0 0 0 0 =1 0 0 0 0 1
1+1 0 0 0 1 0 0 0 1 =2 0 0 0 1 0
1+8 0 0 0 1 1 0 0 0 =9 0 1 0 0 1
1+9 0 0 0 1 1 0 0 1 =A 0 1 0 1 0 Invalid Code
2+0 0 0 1 0 0 0 0 0 =2 0 0 0 1 0
9+9 1 0 0 1 1 0 0 1 = 12 1 0 0 1 0 Wrong BCD Value
0001 1000
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BCD Adder
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value
9+0 1 0 0 1 0 0 0 0 =9 0 1 0 0 1 0 0 0 0 1 0 0 1 =9
9+1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16
9+2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 17
9+3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 18
9+4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 19
9+5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 20
9+6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21
9+7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 22
9+8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 23
9+9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24
+6
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BCD Adder
Correct Binary Adder’s Output (+6)
▪ If the result is between ‘A’ and ‘F’
▪ If Cy = 1
S3 S2 S1 S0 Err
S1
0 0 0 0 0
1 0 0 0 0 S2
1 0 0 1 0 1 1 1 1
S3 1 1
1 0 1 0 1
S0
1 0 1 1 1
1 1 0 0 1
Err = S3 S2 + S3 S1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BCD Adder
x3 x2 x1 x0 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0
0 0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0
Cy S3 S2 S1 S0
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Binary Subtractor
Use 2’s complement with binary adder
▪ x – y = x + (-y) = x + y’ + 1
x3 x2 x1 x0 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0
F3 F2 F1 F0
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Binary Adder/Subtractor
M: Control Signal (Mode)
▪ M=0 F = x + y
▪ M=1 F = x – y
x3 x2 x1 x0 y3 y2 y1 y0 M
A3 A2 A1 A0 B 3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0
F3 F 2 F 1 F 0
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Q. You are presented with a set of requirements under which an
insurance policy will be issued
1. A married female 25 yrs old or above, or
2. A female under 25, or
3. A married male under 25 who has not been involved in a car
accident, or
4. A married man who has been involved in a car accident, or
5. A married male 25 yrs or over who has not been involved in a
car accident
Variables w, x, y and z assume truth value 1 in the following
cases:
• w=1 if the applicant has been involved in car accident
• x=1 if the applicant is married;
• y=1 if the applicant is a male;
• z=1 if the applicant is under 25.
a) Find an algbraic expression that assumes the value 1
whenever the policy should be issued
b) Simplify the above expression and suggest a simpler set of
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
F= xy’z’ + y’z+ w’xyz + wxy + w’xyz’
xy’z’ y’z w’xyz wxy w’xyz’
WX
00 01 11 10
YZ
00 1 1
01 1 1 1 1
11 1 1
10 1 1
F= x + y’z
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
2 Bit Binary Multiplier
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Multiplicand 4 bit Multiplier 3 Bit
A bit of the multiplier is ANDed with
each bit of the multiplicand in as
many levels as there are bits in the
multiplier.
The binary output in each level of
AND gates is added with the partial
product of the previous level to form a
new partial product.
The last level produces the product.
For J multiplier bits and K
multiplicand bits,
We need J X K AND gates and
(J – 1) K -bit adders to produce a
product of (J + K) bits.
If there are more bits then instead of
HA , FA is used
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
MAGNITUDE COMPARATOR
𝐴 = 𝐴3 𝐴2 𝐴 1 𝐴 0 ; 𝐵 = 𝐵3 𝐵 2 𝐵1 𝐵0
Three outputs
)=
A
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
A3 ‘ B 3
A3B3 +A3’B3’
A3B3’
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
