Subj:DIGITAL DESIGN

BITS Pilani
Pilani Campus R K Tiwary
 Digital Logic Families
BITS Pilani R P Jain, Modern Digital Electronics
Pilani Campus
 Logic Families

2.1Types of Devices

2.2Propagation Delays

2.3Power Dissipation

2.4Fan-IN and Fan-OUT

2.5Noise Margin

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Binary Logic(Bi & Uni Polar)
1. Resistor Transistor Logic (RTL)
Saturated family 2. Direct Coupled Transistor Logic (DCTL)
(IC are driven between cut- 3. Integrated Injection logic (I2L)
off and saturation states, 4. Diode Transistor Logic (DTL)
e.g. inverter) 5. Transistor Transistor Logic (TTL)
6. High Threshold Logic (HTL)

1. Schottky TTL
Non-saturated
2. Emitter Coupled Logic (ECL)
family
(transistors are operated between cut-off and active states)

Uni-polar logic 1. PMOS (p-channel) and NMOS (n-channel)

2. CMOS (Complementary MOS)
family

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Classification of Digital ICs
Based on the number of transistors (BJT or MOSFET)
transistors
1. Small Scale Integration (SSI) - 0 to 10

2. Medium Scale Integration (MSI) - 10 to 100

3. Large Scale Integration (LSI) - 100 to 1,000

4. Very Large Scale Integration (VLSI) - 1,000 to 10,000 or thousands gates

5. Super-Large Scale Integration (SLSI) - 10,000 and 100,000 transistors

6. Ultra-Large Scale Integration (ULSI) - more than 1 million transistors

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Characterization of Digital ICs
The various characteristics of digital ICs that can be used to compare their
performance are:

1. Speed of operation (propagation delay, tpLH and tpHL)

2. power dissipation (power consumption under static condition, 0,1;
during the switching intervals or dynamic conditions)
3. Current and voltage parameters (High level input and output
voltages and low level input and output currents; IiH, IoH, IiL, IoL)
4. Noise immunity (measure of how much stray noise voltage the
device can handle without giving any error at the output level)
5. Fan-out (No. of gates that gate in HIGH output state can feed without
voltage dropping by more than the allowable noise margin (NM)H)
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 (a) Fan-out N

M
(b) Fan-in M
N

Vin

50%

t
t t
 Average propagation delay pHL pLH
Vout
90%

50%

10% t
tf tr

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

NOISE immunity

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

TRANSISTOR AS A SWITCH(NPN)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Resistor Transistor Logic (RTL):

Resistor-transistor logic gates

use Transistors to combine
multiple input signals, which
also amplify and invert the
resulting combined signal. Often
A simple N-input RTL NOR Gate
an additional transistor is
included to re-invert the output
signal. This combination
provides clean output signals
and either inversion or non-
inversion as needed.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Resistor Transistor Logic (RTL):

Advantages:
- RTL gates are almost as simple as DL gates, and remain inexpensive.
- Using low power supply for each gate.
- RTL integrated circuits are sometimes used as inexpensive small-
signal amplifiers, or as interface devices between linear and digital circuits.

Limitations:
- RTL gates cannot switch at the high speeds used by today's computers
- These are not designed for linear operation
- low noise margin

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Resistor Transistor Logic (RTL):Logical NOR Gate
VinA VinB Vo
L L H

L H L

H L L

H H L

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Resistor Transistor Logic (RTL):
VinL = 0.2 (LOW input to both transistors)

Under this condition, both transistors will be cutoff, making the output
high. The circuit diagram with circuit models for the cutoff transistors
is shown in Figure. The output voltage then is 3.0 Volts. We will call
this a no-load condition when there is no load connected to the output.

VoH = 3.0 Volts (No-Load)

IinL = 0
VinLmax = 0.5 Volts.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Resistor Transistor Logic (RTL):
INPUT HIGH
In this case we want the transistor to be saturated. Either transistor
saturated will cause the output to go low, to 0.2 volts. This case is
shown in Figure. We show the circuit with one of the transistors
cutoff, although both saturated would produce the same result.
We start by determining the minimum input current that will keep
the transistor in saturation.

the minimum input voltage that will be

guaranteed to be recognized as a "high"
RTL gate with one input high

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Resistor Transistor Logic (RTL):
Any input voltage greater than or equal to 0.866 volts will cause
the transistor to be saturated, and thus be recognized as a "high".
We previously found VinLmax =0.5 volts. Any input voltage between
0.5 and 0.866 is an invalid logic level and the manufacturer
assumes no responsibility if it provide an input voltage in that
range. For the gate with no load, the relationships
between input and output voltages
are presented graphically in Figure.
Noise Margins (High, H and Low, L)
NMH and NML.
Graphical representation of input
voltage ranges and output voltages
for the unloaded RTL gate.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Resistor Transistor Logic (RTL):
wired Logic

Y= Y1.Y2= (A+B)’. (C+D)’= (A+B+C+D)’

The Fan in can be increased by this configuration

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Resistor Transistor Logic (RTL):

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Resistor Transistor Logic (RTL):

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Diode Transistor Logic (DTL):
By letting diodes perform the logical AND or OR function and then
amplifying the result with a transistor, we can avoid some of the limitations of
RTL. DTL takes diode logic gates and adds a transistor to the output, in order
to provide logic inversion and to restore the signal to full logic levels.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Diode Transistor Logic (DTL):
The diode AND function on the front end and the transistor NOT at
the output end. The extra resistors and diodes are used to maintain
appropriate currents, to maintain proper functioning, and to
guarantee certain noise margins.

Diode logic and truth tables Digital NAND circuit

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Diode Transistor Logic (DTL):
If all inputs are high, (+5v), no current will come out of the input
diodes at the input and current will flow down through the first 5K
resistor and through the diodes D1and D2 toward the base of the
transistor. Some current will split off and go down through the
lower 5K resistor to ground. However, most of the current will go
into the base of the transistor causing it to saturate, pulling the
output low, VO = 0.2 Volts. We will show this condition
quantitatively shortly. If one or more of the inputs to the gate are
held low (0.2 V), then the current down through the 5K resistor will
go out the input diode, away from the transistor base. Under
this condition, the transistor will be cutoff and the output will be
high with VO = 5 Volts.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Diode Transistor Logic (DTL):
ANALYSIS WITH INPUT LOW
Quantitatively, we will start with one or more inputs held low, at 0.2 Volts. From
the logic function of the NAND gate, we know that the output is supposed to be
high. Therefore, the transistor must be cutoff. To begin with, we will assume the
two diodes D1 and D2 in series will also be cutoff. All the current coming down
through the 5K resistor must all go out through the input diode, causing it to be
on. The circuit with the models indicated is shown in Figure.

From this circuit we can calculate all

voltages and currents and prove (or
disprove) our assumptions about the
condition of each element.

The voltage at point P is

VP = 0.2 + 0.70 = 0.90 Volts.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Diode Transistor Logic (DTL):
We need to show that this voltage is low enough that the two series diodes and
the transistor will be cutoff. The argument is that if either diode carries current,
then both must. Since 0.9 Volts is not enough across the pair to maintain
conduction, then neither conducts.
Given that the diodes are off, then the voltage at the base of the transistor is zero,
and is also cutoff. We can verify that the input diode is conducting by observing
that current I1 is
I1 = (5-0.9)/5K = 0.82 mA.
This current leaves through the input diode, hence it is on. The current entering
the input terminal is
Iin = - I1 = -0.82 mA
The negative sign occurs because the input current is defined as going into the
terminal.

We can now verify that the output voltage is 5 Volts because the transistor has
been shown to be cutoff. Thus,
VO = 5.0 Volts

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Diode Transistor Logic (DTL):

How high the input voltage

may rise and still keep the
transistor cutoff

indicating that the input diode is still conducting. The maximum

voltage at the input that is guaranteed to be recognized as a low is
VinLmax = 1.9 -0.7 =1.2 Volts.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Diode Transistor Logic (DTL):
The transistor will remain cutoff as long as the voltage at the base does not rise
above 0.5 volts. At this voltage, there will be current down through the lower 5K
resistor to ground. This current must come from the +5 supply down through the
upper 5K resistor and the diodes, D1 and D2. Hence the diodes must be
conducting. This current will be 0.1 mA. The voltage at point P will be
VP = 0.5 + 0.7 + 0.7 = 1.9 Volts
The current I1 is
I1 = (5-1.9)/5K = 0.62 mA
The current going out through the input diode will be
Iin = -(0.62 - 0.1) = -0.52 mA

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Diode Transistor Logic (DTL):
ANALYSIS WITH ALL INPUTS HIGH
When all inputs are high, all current down through the upper 5K resistor
will go toward the base of the transistor, causing it to saturate. The series
diodes will obviously be conducting, and we will show that the input
diodes are cutoff. Figure shows the circuit with these models.

The voltage at point P is

VP = 0.8 + 0.7 + 0.7 = 2.2 volts
Thus, I1 is
I1 = (5-2.2)/5K = 0.56 mA

Current going down through the

5K resistor will be
I2 = 0.8/5K = 0.16 mA
The base current then is
IB = 0.56 - 0.16 = 0.4 mA DTL circuit model with inputs high

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Diode Transistor Logic (DTL):
If the transistor is to be saturated, the maximum collector current is
ICmax = βIB = 30 * 0.4 mA = 12.00 mA

at saturation, the current coming down through the 2.2K collector resistor is
I3 = (5-0.2)/2.2K = 2.182 mA
this current is much less than the maximum saturation current and
we see that with no load, the transistor will, indeed, be in saturation.

In fact, there is excess capacity in collector saturation current. This

excess capacity can be used to sink external load current. This
current is called Io or load current. The maximum load current this
gate can sink is
IoLmax = 12.00 mA - 2.182 mA = 9.818 mA
Note that this current is entering the terminal of the gate, hence, is positive.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Diode Transistor Logic (DTL):
CALCULATION OF FANOUT
If several load gates are connected to the output terminal of the gate we are
looking at, we need to look at the current output drive capability compared to the
input current requirements of the load gates. Because the input current is zero
when high, an infinite number of load gates can be driven when high. However,
the DTL gate requires current when the input is low. This situation is shown in
Figure. IinLmax = - 0.82 mA. Negative meaning that it is coming out of the input
terminal. The output of a gate can sink 9.818 mA when it is low.
  𝐼 𝑂𝐿𝑚𝑎𝑥 9.818
𝐹𝑎𝑛𝑜𝑢𝑡 𝑁≤ = =11.97 ≅ 12
𝐼 𝐼𝑁𝑙𝑜𝑤 0.82

Comparison of Vout and Vin

DTL driver gate with N identical DTL load gates voltages for DTL gate.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Exaplanation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diode Transistor Logic

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Thank You

Wednesday, January 05, 2 BITS Pilani, Pilani Campus