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Introduction To Uvm

This document provides an introduction and overview of the Universal Verification Methodology (UVM) over the course of a 7-day training agenda. UVM is an open-source verification methodology and class library built on SystemVerilog that provides reusable verification components and a standardized architecture. It offers advantages like modularity, phasing for synchronization, reporting and configuration mechanisms, and separation of tests from testbenches to enable reuse.

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Rajesh Panda
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251 views

Introduction To Uvm

This document provides an introduction and overview of the Universal Verification Methodology (UVM) over the course of a 7-day training agenda. UVM is an open-source verification methodology and class library built on SystemVerilog that provides reusable verification components and a standardized architecture. It offers advantages like modularity, phasing for synchronization, reporting and configuration mechanisms, and separation of tests from testbenches to enable reuse.

Uploaded by

Rajesh Panda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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INTRODUCTION

TO
UVM METHODOLOGY
AGENDA
DAY TOPIC
DAY 1 Introduction to UVM methodology & UVM Factory
DAY 2 UVM Phases & Stimulus modeling
DAY 3 Reporting Mechanism
DAY 4 TLM Overview & UVM Configuration
DAY 5 Virtual Interface & Project Overview
DAY 6 Creating TB Component & UVM Sequence
DAY 7 Virtual Sequence & Sequencer
WHAT IS UVM?
• Universal Verification Methodology
– A methodology and a class library for building advanced reusable
verification components
• Relies on strong, proven industry foundations
– The core of the success is adherence to a standard (architecture,
stimulus creation, automation, factory usage, etc)
• UVM is a methodology based on SystemVerilog language
• UVM consists of a defined methodology in terms of architecting
testbenches and test cases  
• Comes with a  library of classes that helps in building efficient constrained
random testbenches easily.
ADVANTAGES OF UVM
• Modularity and Reusability
– The methodology is designed as modular components (Driver, Sequencer, Agents , env etc)  which enables
reusing components across  unit level to multi-unit or chip level verification as well as across projects.
• Phasing
– Helps in synchronization of each and every component before proceeding to next phase.
• Reporting mechanism
– Helps in debugging environment
– By changing the verbosity , printing of messages can be controlled
– Like SV we don't have to give display command again and again within a class.
• Factory mechanism
– Creating each components using factory  enables them to be overridden in different tests or environments
without changing underlying code base
• Configuration class
– Easily configuring different testbench components based on which verification environment uses it and
without worrying about how deep any component is in testbench hierarchy
• Separating Tests from Testbenches
– Tests in terms of stimulus/sequencers are kept separate from the actual testbench hierarchy
– There can be reuse of stimulus across different units or across projects
ORIGIN OF UVM
Vera RVM

VMM
VMM 1.2

SV
AVM
OVM UVM

E ERM URM
EVOLUTION OF UVM

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