Chapter 6

Functions of
Combinational Logic
Outlines
Adders
Decoders
Encoders
Multiplexers
Demultiplexers
Parity generator/checkers
Adders
• Digital systems perform a variety of information-processing
tasks.
• Among the functions encountered are the various arithmetic
operations.
• The most basic arithmetic operation is the addition of two
binary numbers.
• Adders are important in computers and also in other types of
digital systems in which numerical data are processed.
Half adder
 The half-adder is a combinational circuit that performs the
addition of two bits.
 This circuit needs two binary inputs and two binary outputs
the sum output and carry . The logic symbol and truth table
for the half adder is shown below.

A B S The sum output expression is:

0 0 0 0
0 1 1 0
1 0 1 0 The carry output:
1 1 0 1
Full Adder
 The full adder is a combinational circuit that performs the addition of
three bits (two significant bits and previous carry).
 It consists of three inputs and two outputs, two inputs are the bits to be
added, the third input represents the carry from the previous position.
 Two outputs are necessary because the arithmetic sum of three binary
digits ranges in value from 0 to 3, and binary representation of 2 or 3
needs two bits.
 The basic difference between a full-adder and a half-adder is that the
full-adder accepts an input carry.
 The full adder is usually a component in a cascade of adders, which
add 8, 16, etc., binary numbers.
Full Adder… Sum S A
AB
Full Adder Truth Table C-in 00 01 11 10
0 2 6 4
Inputs Outputs 0 1 1
A B S 1
1
1
3 7
1
5
C-in

0 0 0 0 0
B
0 0 1 1 0 The sum output:
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
Carry C-out A
1 0 1 0 1 AB
C-in 00 01 11 10
1 1 0 0 1 0 2 6 4
0 1
1 1 1 1 1 3 7 5
1
1 1 1 1 C-in

S(A,B, ) = S (1,2,4,7) B
(A, B, C-in) = S (3,5,6,7)
𝑪𝒐𝒖𝒕 = 𝑨𝑩+ ( 𝑨 ⨁ ­𝑩 ) 𝑪𝒊𝒏
Full Adder…
 Implementation of full-adder with two half adders and an
OR gate

Figure: Full-Adder logic diagram

Binary Adder
• A binary adder is a digital circuit that produces the arithmetic sum
of two binary numbers.
• The binary adder can be constructed with full adders connected in
cascade, with the output carry from each full adder connected to
the input carry of the next full adder in the chain.
• To add two binary numbers, a full-adder (FA) is required for each bit
in the numbers.
• For instance; For 2-bit numbers, two full adders are needed; for 4-
bit numbers, four full adders are used; and so on.
• The four-bit adder is a typical example of a standard component. It
can be used in many application involving arithmetic operations.
 Binary Adder…
4-bit Binary Adder Inputs to be added
Adds two 4-bit numbers: A3A2A1A0 B3B2B1B0

4-bit
C4
producing the sum C-out
Adder
C-in C0 =0

S = S3 S2 S1 S0, and
from the most significant
S3 S2 S1 S0
position j=3.
Sum Output
Data inputs to be added
A3 B3 A2 B2 A1 B1 A0 B0

Full C3 Full C2 Full C1 Full

C4 C-out C-in C-out C-in C-out C-in C-out C-in C0 =0
Adder Adder Adder Adder

S3 S2 S1 S0
Sum output
Binary Adder…
 Example: Consider the addition of two four-bit binary
numbers, , .

Subs. i 3 2 1 0
0 1 1 0
A 1 0 1 1
B 0 0 1 1
S 1 1 1 0
0 0 1 1
Carry Propagation
Parallel adders can be placed into two categories based on the
way in which internal carries from stage to stage are handled.
i) Ripple carry
ii) Look-ahead carry
Externally, both types of adders are the same in terms of inputs
and outputs, and their difference is the speed at which they can
add numbers
The look-ahead carry adder is much faster than the ripple carry
adder.
The Ripple Carry Adder
• A ripple carry adder is one in which the carry output of each
full-adder is connected to the carry input of the next higher-
order stage (a stage is one full-adder).
• The sum and the output carry of any stage cannot be produced
until the input carry occurs; this causes a time delay in the
addition process.
• The carry propagation delay for each full-adder is the time
from the application of the input carry until the output carry
occurs, assuming that both inputs are already present.
The Look-Ahead Carry Adder
 The speed with which an addition can be performed is limited
by the time required for the carries to propagate, or ripple,
through all the stages of a parallel adder.
 One method of speeding up the addition process by
eliminating this ripple carry delay is called look-ahead carry
addition.
 The look-ahead carry adder anticipates the output carry of
each stage, and based on the inputs, produces the output
carry by either carry generation or carry propagation.
The Look-Ahead Carry Adder…
 Carry generation:
 occurs when an output carry is produced (generated)
internally by the full-adder.
 A carry is generated only when both input bits are 1s.
 Thus, the generated carry, Cg, is expressed as the AND
function of the two input bits, A and B.
The Look-Ahead Carry Adder
 Carry propagation:
 occurs when the input carry is rippled to become the
output carry.
 An input carry may be propagated by the full-adder when
either or both of the input bits are 1s.
 The propagated carry , is expressed as the OR function of
the input bits.
Decoder
• Discrete quantities of information are represented in digital systems
by binary codes.

• A binary code of bits is capable of representing up to distinct

elements of coded information.

• A decoder is a logic circuit that accepts a set of inputs that represents

a binary coded information and activates only the output that
corresponds to the input code.

• In other words, a decoder circuit looks at its inputs, determines

which binary number is present there, and activates the one output
that corresponds to that number; all other outputs remain inactive.
Con’t…
• In its general form, a decoder has an -bit binary code
applied to its inputs and an -bit, binary code appearing at
the output.

Figure: Black box with input lines and 2n output lines

Con’t…
The Basic Binary Decoder
 If an active-HIGH output (one of the output will high and the rest
will be low) is required for each decoded number, the entire
decoder can be implemented with AND gates and inverters.
 If an active-LOW output (one of the output will low and the rest
will be high) is required for each decoded number, the entire
decoder can be implemented with NAND gates and inverters.

Fig. Decoding logic for the binary code 1001 with an active-HIGH output.
A 2-to-4 Decoder (Active-HIGH)
 2 inputs designated by (A1, A0) and,
 22 = 4 outputs designated by (D3, D2, D1, D0)
Truth Table Logic Diagram
Inputs Outputs

0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

• Only one output can be equal to 1 at any given time, all other outputs are
equal to 0.
• The output whose value is equal to 1 represents the minterm selected by
inputs & .
A 3-to-8 Decoder
• 3 inputs (A2 ,A1, A0, )
• 23 = 8 outputs
Truth Table

Fig. Black box with 3-

inputs & 8-outputs
Con’t…
 This decoder can be referred to in several ways.

– It can be called a 3-line-to-8-line decoder, because it has

three input lines and eight output lines.
– It could also be called a binary-to-octal decoder or
converter because it takes a three bit binary input code and
activates the one of the eight outputs corresponding to that
input code.
– It is also referred to as a 1-of-8 decoder, because only 1 of
the 8 outputs is activated at one time.
Con’t…

Fig.: 3-to-8 line decoder

Decoder-Based Combinational Circuits
Implementing functions with decoder
• Any combinational logic circuit with n inputs and outputs can
be implemented with an n-to-2n-line decoder and m OR gates.
• Procedure:

– Express the given Boolean function in sum of minterms

– Choose a decoder to generate all the minterms of the input
variables.
• Select the inputs to each OR gate from the decoder outputs
according to the list of min-term for each function.
Decoder-Based Combinational Circuits
Example: design of full adder using decoder

• 3 inputs and 8 possible minterms

• 3-to-8 decoder can be used for implementing this circuit
X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Encoder
• An encoder is a combinational logic circuit that essentially
performs a “reverse” of decoder functions.
• An encoder accepts an active level on one of its inputs,
representing digit, such as a decimal or octal digits, and
converts it to a coded output such as BCD or binary.
• Encoders can also be devised to encode various symbols and
alphabetic characters.
• The process of converting from familiar symbols or numbers
to a coded format is called encoding.
• An encoder has 2n (or fewer) input lines, only one of which
input is activated at a given time and produces an n-bit output
code, depending on which input is activated.
Con’t…
. 2n-to-n
2 inputs
n
. . n
. Encoder outputs
 8-to-3 Encoder
•Description:
•23 = 8 inputs, 3 outputs
D0 •one input =1, others = 0’s at a
D1
D2 A0
time
D3 8-to-3
D4 Encoder
A1 •Each input generate unique
A2
D5
binary code
D6
D7
8-to-3 Encoder (truth table)
inputs outputs
D D D D D D D D A2 A1 A0
7 6 5 4 3 2 1 0
D0
D1 0 0 0 0 0 0 0 1 0 0 0
D2
D3 8-to-3 A0
0 0 0 0 0 0 1 0 0 0 1
A1
D4 Encoder A2 0 0 0 0 0 1 0 0 0 1 0
D5
D6 0 0 0 0 1 0 0 0 0 1 1
D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 8-to-3 Encoder (truth table)
inputs outputs
D D D D D D D D A2 A1 A0
7 6 5 4 3 2 1 0
1 D0
0 D1 0 0 0 0 0 0 0 1 0 0 0
0 D2
0 D3 8-to-3 A0 0
0
0 0 0 0 0 0 1 0 0 0 1
0 A1
0
D4 Encoder A2 0 0 0 0 0 0 1 0 0 0 1 0
0 D5
0 D6 0 0 0 0 1 0 0 0 0 1 1
D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 8-to-3 Encoder (truth table)
inputs outputs
D D D D D D D D A2 A1 A0
7 6 5 4 3 2 1 0
0 D0
1 D1 0 0 0 0 0 0 0 1 0 0 0
0 D2
0 D3 8-to-3 A0 1
0
0 0 0 0 0 0 1 0 0 0 1
0 A1
0
D4 Encoder A2 0 0 0 0 0 0 1 0 0 0 1 0
0 D5
0 D6 0 0 0 0 1 0 0 0 0 1 1
D7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
8-to-3 Encoder (truth table)
inputs outputs
D D D D D D D D A2 A1 A0
7 6 5 4 3 2 1 0

D0
0 0 0 0 0 0 0 1 0 0 0
D1 0 0 0 0 0 0 1 0 0 0 1
D2 A0
D3
8-to-3 A1
0 0 0 0 0 1 0 0 0 1 0
D4 Encoder A2 0 0 0 0 1 0 0 0 0 1 1
D5
D6 0 0 0 1 0 0 0 0 1 0 0
D7 0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
8-to-3 Encoder (truth table)
inputs outputs
D D D D D D D D A2 A1 A0
7 6 5 4 3 2 1 0
D0
D1 0 0 0 0 0 0 0 1 0 0 0
D2
8-to-3 A0 0 0 0 0 0 0 1 0 0 0 1
D3 A1
D4 Encoder A2 0 0 0 0 0 1 0 0 0 1 0
D5
D6
0 0 0 0 1 0 0 0 0 1 1
D7 0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 8-to-3 Encoder (equations)
inputs outputs
D0 D D D D D D D D A2 A1 A0
D1
7 6 5 4 3 2 1 0
D2 A0
8-to-3
D3 A1 0 0 0 0 0 0 0 1 0 0 0
D4 Encoder A2
D5 0 0 0 0 0 0 1 0 0 0 1
D6
D7 0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
Output equations:
A0 = ? 0 0 1 0 0 0 0 0 1 0 1
A1 = ? 0 1 0 0 0 0 0 0 1 1 0
A2 = ? 1 0 0 0 0 0 0 0 1 1 1
Note: This truth table is not complete! Why?
 8-to-3 Encoder (equations)
inputs outputs
D D D D D D D D A2 A1 A0
7 6 5 4 3 2 1 0
D0
D1 0 0 0 0 0 0 0 1 0 0 0
D2 A0
D3 8-to-3 A1 0 0 0 0 0 0 1 0 0 0 1
D4 Encoder A2
D5 0 0 0 0 0 1 0 0 0 1 0
D6
D7
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
Output equations:
0 0 1 0 0 0 0 0 1 0 1
A0 = D 1 + D 3 + D 5 + D 7
0 1 0 0 0 0 0 0 1 1 0
A1 = ?
1 0 0 0 0 0 0 0 1 1 1
A2 = ?
 8-to-3 Encoder (equations)
inputs outputs
D D D D D D D D A2 A1 A0
7 6 5 4 3 2 1 0
D0
D1 0 0 0 0 0 0 0 1 0 0 0
D2 A0
D3 8-to-3 A1 0 0 0 0 0 0 1 0 0 0 1
D4 Encoder A2
D5 0 0 0 0 0 1 0 0 0 1 0
D6
D7
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
Output equations: 0 0 1 0 0 0 0 0 1 0 1
A0 = D 1 + D 3 + D 5 + D 7
0 1 0 0 0 0 0 0 1 1 0
A1 = D 2 + D 3 + D 6 + D 7
1 0 0 0 0 0 0 0 1 1 1
A2 = ?
 8-to-3 Encoder (equations)
inputs outputs
D D D D D D D D A2 A1 A0
7 6 5 4 3 2 1 0
D0
D1 0 0 0 0 0 0 0 1 0 0 0
D2 A0
D3 8-to-3 A1 0 0 0 0 0 0 1 0 0 0 1
D4 Encoder A2
D5 0 0 0 0 0 1 0 0 0 1 0
D6
D7
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
Output equations:
0 0 1 0 0 0 0 0 1 0 1
A0 = D 1 + D 3 + D 5 + D 7
0 1 0 0 0 0 0 0 1 1 0
A1 = D 2 + D 3 + D 6 + D 7
1 0 0 0 0 0 0 0 1 1 1
A2 = D 4 + D 5 + D 6 + D 7
 8-to-3 Encoder (circuit)
D1
D0 D3
D1 D5 A0
D2 A0 D7
D3 8-to-3 A1 D2
D4 Encoder A2 D3
A1
D5 D6
D6 D7
D7 D4
D5 A2
D6
Output equations: D7

A0 = D 1 + D 3 + D 5 + D 7
A1 = D 2 + D 3 + D 6 + D 7
A2 = D 4 + D 5 + D 6 + D 7
 8-to-3 Encoder (limitations)
inputs outputs
Two Limitations:
1. Two or more inputs = 1 D D D D D D D D A2 A1 A0
• Example: D3 = D6 = 1 7 6 5 4 3 2 1 0

• A2A1A0 = 111 0 0 0 0 0 0 0 1 0 0 0
2. All inputs = 0 0 0 0 0 0 0 1 0 0 0 1
• Same as D0 =1
0 0 0 0 0 1 0 0 0 1 0
Output equations: 0 0 0 0 1 0 0 0 0 1 1
A0 = D1 + D3 + D5 + D7 0 0 0 1 0 0 0 0 1 0 0
A1 = D2 + D3 + D6 + D7 0 0 1 0 0 0 0 0 1 0 1
A2 = D4 + D5 + D6 + D7 0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 Priority Encoder
• A priority encoder is an encoder that includes
the priority function
• Address the previous two limitations
1. Two or more inputs = 1
– Consider the bit with highest priority
2. All inputs = 0
– Add another output v to indicate this
combination
 4-to-2 Priority Encoder
Description:
• 22 = 4 inputs, 2 + 1 outputs
• Two or more 1’s take This is a condensed truth table!
highest It has only 5 rows instead of 16!
priority
inputs outputs Row 3 = 2 combinations
V Row 4 = 4 combinations
Row 5 = 8 combinations
0 0 0 0 X X 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
 4-to-2 Priority Encoder
inputs outputs
D D D D A1 A0 V
3 2 1 0

0 0 0 0 X X 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1

Equations:
A0= D3 + D1 D2’
A1= D2 + D3
V= D0 + D1+D2+ D3
 4-to-2 Priority Encoder
Equations:
A0= D3 + D1 D2’
A1= D2 + D3
V= D0 + D1+D2+ D3

Fig. Logic diagram of 4-to-2 priority encoder

Multiplexer
• A multiplexers (MUX) is a device that allows digital
information from several sources to be routed onto a single
line for transmission over that line to a common destination.

• The basic multiplexers has several data input lines and a

single output line.

• It also has data- select inputs, which permit digital data on

any one of the inputs to be switched to the output line.
Con’t…
• A modern stereo system may have a switch that selects music
from one of four sources: a cassette tape, CD, a radio tuner , or
an auxiliary input such as audio from a VCR or DVD. The
switch selects one of the electronic signals from one of these
four sources and sends it to the power amplifier and speakers.

• In simple terms, this is what a multiplexer (MUX) does; it

selects one of several input signals and passes it on to the
output.
Con’t…

Fig. Functional diagram of MUX

 2x1 MUX
• A 2x1 multiplexer (MUX) will have 2 input lines and 1 select
line

D0 2x1
Y 0
MUX
D1
1

S0
• Y=D0 for S0=0, and Y=D1 for S0=1
• Minimizing the overall expression will result in: Y = S0’.D0 +
S0.D1
 4x1 MUX
• A 4x1 MUX will have 4 input lines (D0, D1, D2, D3) and 1 output Y
with 2 Select Lines (S0, S1)
• The output for different select values is defined as:
• S0S1 = 00, Y = D0
• S0S1 = 01, Y = D1 D0

• S0S1 = 10, Y = D2 D1
4x1
D2 MUX Y
• S0S1 = 11, Y = D3
D3

S1 S0
• Y = S1S0D0 + S1S0D1 + S1S0D2 + S1S0D3
• The output Y depends on the minterms of the Select lines
Con’t…

48
MUX-based Design
• An efficient method for implementing a Boolean function of n
variables with a MUX that has n-1 selection inputs and 2 n-1 data
inputs is given below:
– List the Boolean function in a truth table

– Apply the first n-1 variables in the table to the selection inputs of
the MUX.
– For each combination of the selection variables, evaluate the
output as a function of the last variable. This function can be 0,1,
the variable, or the complement of the variable. Apply these
values to the data inputs in the proper order.
Example 1
Implement the Boolean function F=x’y’z +x’yz’ + xyz’ + xyz
using a suitable MUX

0
1

2
3

50
 Example 1 Con’t…
• The two variables x and y are applied to the selection lines in
that order; x is connected to the S1 input and y to the S0 input.

• The values for the data input lines are determined from the truth
table of the function
– For ex., when xy=00, output F is equal to z because F=0 when
z=0 and F=1 when z=1. This requires that variable z is applied
to the data input 0

51
Example 2
Implement the Boolean function F=A’B’C’D+A’B’CD+A’BC’D’
+AB’CD+ABC’D’+ABC’D+ABCD’+ABCD using a suitable
MUX

0
1
2
3
4
5
6
7

52
DeMultiplexer
• A DEMULTIPLEXER (DEMUX) basically reverses the
multiplexing function.

• It takes data from one line and distributes them to a given

number of output lines.

• For this reason, the demultiplexers is also known as a data

distributor.

• It has one input line, the input from which is transmitted to

one of output lines.
 General demultiplexer

Functional diagram:- The large arrow indicates one or

more lines. The select i/p code
determines to which output the
DATA input will be transmitted

In other words, the

demultiplexer takes one data
input source and selectively
distributes it to 1 of N output
channels just like
multiposition switch.
54
 1x4 DeMUX

D0
1x4 D1
E DeMUX D2
D3

S0 S1

• The circuit has an input E, the outputs are given by:

D0 = E, if S0S1=00 D0 = S1’S0’ E
D1 = E, if S0S1=01 D1 = S1’S0 E
D2 = E, if S0S1=10 D2 = S1S0’ E
D3 = E, if S0S1=11 D3 = S1S0 E
1x4 DeMUX

56
The serial data input waveform (Data in) and data select inputs (So and S1)
and
the corresponding data output waveforms (D0 through D3) are shown
below

57