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LATCH UP CMOS Inverter

Latch-up occurs in CMOS chips when a low-impedance path is generated between the power supply rail and ground due to the interaction of parasitic bipolar junction transistors (BJTs). These BJTs form a silicon-controlled rectifier (SCR) with positive feedback that can damage the chip through excessive current. Guidelines for avoiding latch-up include reducing the gains of the parasitic BJTs, adding guard rings around transistors, and properly spacing n- and p-channel transistors to prevent triggering of the SCR.

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GIRISH GIDAYE
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257 views19 pages

LATCH UP CMOS Inverter

Latch-up occurs in CMOS chips when a low-impedance path is generated between the power supply rail and ground due to the interaction of parasitic bipolar junction transistors (BJTs). These BJTs form a silicon-controlled rectifier (SCR) with positive feedback that can damage the chip through excessive current. Guidelines for avoiding latch-up include reducing the gains of the parasitic BJTs, adding guard rings around transistors, and properly spacing n- and p-channel transistors to prevent triggering of the SCR.

Uploaded by

GIRISH GIDAYE
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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CMOS VLSI Design 4th Ed. 5
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CMOS VLSI Design 4th Ed. 7
• Latch-up is defined as the generation
of a low-impedance path in CMOS
chips between the power supply rail
and the ground rail due to interaction
of parasitic pnp and npn bipolar
transistors.
• These BJTs form a silicon-controlled
rectifier (SCR) with positive feedback
and virtually short circuit the power rail
to-ground, thus causing excessive
current flows and even permanent
device damage. 8
• In the equivalent circuit, Q1 is a pnp transistor whose
base is formed by the n-well with its base-to-collector
current gain as high as several hundreds. Q2 is a
lateral npn transistor with its base formed by the p-
type substrate with its base-to-collector current gain a
few tenths to tens.
• Rwell represents the base-to-collector current gain of
this lateral transistor may parasitic resistance in the n-
well structure with its value ranging from 1 k to 20
kohm.
• The substrate resistance Rsub strongly depends on
the substrate structure, whether it is a simple p- or p-
epitaxial layer grown on top of the p+ substrate which
acts as a ground plane. In the former case Rsub can
be as high as several hundred ohms, whereas in the
latter case the resistance can be as low as a few
ohms.
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• To examine the latch-up event, first assume that the parasitic
resistances Rwell and Rsub are sufficiently large so that they
can be neglected (open circuit).
• Unless the SCR is triggered by an external disturbance, the
collector currents of both transistors consist of the reverse
leakage currents of the collector-base junctions and therefore,
their current gains are very low.
• If the collector current of one of the transistors is temporarily
increased by an external disturbance, however, the resulting
feedback loop causes this current perturbation to be multiplied
by (β1β2). This event is called the triggering of the SCR.

• Once triggered, each transistor drives the other transistor with


positive feedback, eventually creating and sustaining a low-
impedance path between the power and the ground rails,
resulting in latch-up.

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• Some of the causes for latch-up are:
• * Slewing of VDD during initial start-up can
cause enough displacement currents
due to the well junction capacitance in the
substrate and the well. If the slew rate is
large enough, latch-up can be induced.

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• Large currents in the parasitic SCR in CMOS chips can
occur when the input or output signal swings either far
beyond the VDD level or far below the Vss (ground)
level, thus injecting a triggering current. Such
disturbance can happen due to impedance mismatches
in transmission lines of high-speed circuits.
• * ESD stress can also cause latch-up by the injection of
minority carriers from the clamping device in the
protection circuit into either the substrate or the well.
• * Sudden transients in power or ground buses due to
simultaneous switching of many drivers may turn on a
BJT in SCR.
• * Leakage currents in well junctions can cause large
enough lateral currents.
• * Radiation due to X-rays, cosmic rays, or alpha
particles may generate enough electron-hole pairs in
both the substrate and well regions and thus trigger the
SCR.
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• Guidelines for Avoiding Latch-Up
• * Reduce the gains of BJTs by lowering the
minority carrier lifetime through gold doping of
the substrate (but without causing excessive
leakage currents) or reducing the minority
carrier injection efficiency of BJT emitters by
using Schottky source/ drain contacts.

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CMOS VLSI Design 4th Ed. 15
CMOS VLSI Design 4th Ed. 16
• Use p+ guardband rings connected to
ground around nMOS transistors and n+
guard rings connected to VDD around
pMOS transistors to reduce R and RSUb
and to capture injected minority carriers
before they reach the base of the parasitic
BJTs.
• Place substrate and well contacts as
close as possible to the source
connections of MOS transistors to
reduce the values of R and Rsub*
• Use minimum area p-wells (in case of
twin-tub technology or n-type substrate) so
that the p-well photocurrent can be
minimized during transient pulses.
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• Avoid the forward biasing of source/drain
junctions so as not to inject high currents;
the use of a lightly doped epitaxial layer on
top of a heavily doped substrate has the
effect of shunting lateral currents from the
vertical transistor through the low
resistance substrate.
• Layout n- and p-channel transistors such
that all nMOS transistors are placed close to
Vss and pMOS transistors are placed close
to VDD rails.
• Also maintain sufficient spacings between
pMOS and nMOS transistors.
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END

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