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Module 7

The document provides an introduction to high-level synthesis (HLS), which transforms behavioral specifications into register-transfer level (RTL) implementations. It describes the key steps in HLS as scheduling, allocation, binding, and controller/datapath generation. Scheduling assigns operations to control steps. Allocation selects functional units and storage elements from a library. Binding assigns operations to functional units and variables to storage elements. The document discusses the different types of scheduling problems and explains the goals of allocation and binding.

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26 views12 pages

Module 7

The document provides an introduction to high-level synthesis (HLS), which transforms behavioral specifications into register-transfer level (RTL) implementations. It describes the key steps in HLS as scheduling, allocation, binding, and controller/datapath generation. Scheduling assigns operations to control steps. Allocation selects functional units and storage elements from a library. Binding assigns operations to functional units and variables to storage elements. The document discusses the different types of scheduling problems and explains the goals of allocation and binding.

Uploaded by

Kailash s
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module 7

Introduction to HLS: Scheduling, Allocation and Binding Problem


Contents
• Need of HLS
• Introduction of HLS
• Scheduling
• Allocation
• Binding
Introduction
• Any VLSI design we start with specifications and the first step is to obtain the Register
Transfer Level (RTL) circuit.
• RTL circuit is obtained from specifications using High Level Synthesis (HLS) algorithms.
As specifications are processed by HLS algorithms, they need to be represented using some
modeling language.
• Control and Data Flow Graph (CDFG), is one of the most widely accepted modeling
paradigm for specifications that are processed by HLS tools.
• Transformation techniques in the CDFGs, which lead to efficient circuit implementation in
terms of area, frequency, power etc. HLS takes as input, the optimized CDFG, performs
Scheduling, Allocation, Binding and generates RTL design.
Introduction to HLS
A behavioral description (i.e., functional specifications) is used as the starting point
for HLS. It specifies the behavior in terms of operations, assignment statements,
and control constructs in a Hardware Description Language (HDL) .
I. The first step in HLS is compilation of the HDL and transformation into an
internal representation.
• Most HLS techniques use Control and Data Flow Graph (CDFG) as the
representation, because it contains both the data flow and the control flow.
• This process also includes a series of compiler like optimizations namely, dead
code elimination, redundant expression elimination etc.
• Further, it also applies hardware-library specific transformations such as, use of
incrementers instead of adders, use of shifters instead of multipliers etc.
Sometimes we call these steps as pre-processing phase for HLS, where the
optimized CDFG is provided to HLS engine.

II. The second step of the HLS, which plays a key role in transforming a CDFG
(i.e., behavioral) representation into a RTL (i.e., structural) representation, is
operation-scheduling (called just “scheduling” in HLS terminology).
• Scheduling involves assigning operations of the CDFG to so-called control steps. A
control step usually corresponds to a cycle of the system clock, the basic time unit
of a synchronous digital system.

III. The third step is Allocation, which chooses functional units and storage elements
from the design library.
• The design library has several alternatives for a given functional unit or a storage
unit.
• For example, for a functional unit like adder, there can be many options like ripple-
carry adder, carry-look-ahead-adder etc.
• Similarly, for storage elements there can be different types of registers like registers
with only resets, registers with both pre-sets and resets, registers with pre-sets, resets
and load etc.
• Among the alternatives, the allocation algorithm must select the one that matches the
design constraints best and maximizes the optimization objective.
IV. The fourth step is Binding. After the functional operations and storage operations
are scheduled and components from design library are selected for such operations
(allocation), then comes the role of binding.
• Binding assigns operations to functional units, variables to storage elements and
data transfers to wires or buses such that data can be correctly computed and passed,
according to the scheduling.
V. The final step of HLS is data-path and controller generation. Depending upon the
scheduling and the binding information, interconnection between the circuit
modules of the data-path components are set up; this is called data-path generation.
• Further, an FSM is generated to control all the micro-operations required to control
data-flow in the data-path; this is called controller generation.
Scheduling Problem
• The scheduling problem involves determining the sequence in which the operations
are executed to produce a control step schedule, which specifies the operations that
execute in each control step.
The following four types of scheduling problems
• Un-Constrained Scheduling (UCS) problem
• Time Constrained Scheduling (TCS) problem
• Resource Constrained Scheduling (RCS) problem
• Time-Resource Constrained Scheduling (TRCS) problem
Allocation Problem

• Once a schedule is made (i.e., type of operators are determined along with their
quantity), the allocation task determines the “exact” operator modules, available in
the design library, to be used in implementation of the operators. Also, the area,
power, frequency is determined after allocation.
• • It has description regarding the type of modules (i.e., functionality), sub-types
(namely, fast, slow, typical etc.), area, power, frequency etc. In case of a modern
sub-micron technology, a design library has many more entries namely, leakage
power, current etc.
Binding

• After all the operations are scheduled and allocation is done, we get information regarding
exact type of circuit modules (from the design library) to be used and their numbers.
• We have seen in the allocation step, that operations in a control step are performed by
different modules, however, modules are shared between operations (of same type) that are in
different control steps.
• Further, to store variables (a,b,c,d,e) and intermediate results (temp1,temp2.temp3) we need
registers. Like operational modules, registers can be shared, which do not lie in same control
step. All the above-mentioned steps (after scheduling and allocation) fall under Binding.
The binding task (also called resource-sharing step) assigns the operations and
variables to hardware modules. A resource such as an operational module or register
can be shared by different operations, data accesses, or data transfers if they are
mutually exclusive.
For example, two operations assigned to two different control steps are mutually
exclusive since they will never execute simultaneously; hence, they can be binded to
the same hardware unit. Binding can be classified into three sub-functions:
Storage binding: This step assigns input, output and temporary variables to registers
units. Two variables that are not alive simultaneously (i.e., not required in overlapping
control steps) in a given control step can be assigned to the same register.
Functional-unit binding: This binding step assigns operations to operational modules
(like adder, multiplier etc.). Two operations of same type that are not in a single control
step can be assigned to the same operational module.
Interconnection binding: This step assigns an interconnection unit such as a
multiplexer or a bus to a data transfer.
Thank-You

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