PROJECT – FIRST REVIEW

Design and Implementation of 32 bit RISC processor

using verilog .
Presented By: Y. Suryaprakash (20341A04J2)
B. Venugopal (20341A04I6)
GMR Institute of Technology

D. Revathipathi (20341A04F3)
M. Gowtham Durga prasad (21345A0413)
T. Hariprasad (20341A04H7)

Supervisor: Dr. SK. Rizwan

Assistant Professor
ECE Dept, GMRIT

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 INTRODUCTION
• RISC Stands for Reduced Instruction Set Computer.
• RISC processor has the less number of Instructions compared to the CISC
processor.
• Due to less number of instructions, it has less number of transistors which
leads to decrease in Area and Size.
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• Power Consumption is directly proportional to number of transistors,

Hence power consumption is less in RISC processor compared to CISC
processor.
• We can derive the instructions of CISC processor by using the
Fundamental Instructions which are used in RISC processor.
• In VLSI our main motto is to decrease power consumption, Area and to
increase performance.
• Hence, we choose RISC processor over CISC processor.

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 OBJECTIVE OF THE PROJECT
1. Reduced Instruction Set Computer is a Microprocessor that executes small
and simple instructions in a similar time.
2. RISC processor is to provide an efficient, and high-performance architecture
by simplifying the instruction set, optimizing instruction execution, and
minimizing hardware complexity.
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3. RISC reduces the complexity of the instructions. RISC uses simple

instructions.
4. Fetch, Decode, Execute all are completed in a single clock pulse.
5. These make RISC processors well-suited for a wide range of applications,
including embedded systems, mobile devices, and general-purpose
computing.

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 LITERATURE SURVEY
[1].Jikku Jeemon “Low Power Pipelined 8-bit RISC Processor Design
and Implementation on FPGA”International Conference on
Control,Instrumentation, Communication and Computational Technologies
(lCCICCT) ,2015.
 This article presents the design and implementation of a simple 8-bit RISC
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processor using the RISC (Reduced Instruction Set Computing) design

technique.
 The processor features an 8-bit Arithmetic Logic Unit (ALU), two 8-bit
I/O ports, eight 8-bit general-purpose registers, and a 4-bit flag register for
zero, carry, borrow, and parity flags.
 Pipelining is used in the processor to improve performance, allowing one
instruction to be executed per clock cycle.
 The processor follows the Harvard architecture, with separate instruction
and data memory.
 The instruction set of the processor is designed to be simple, containing
only 29 instructions, which makes it easy to learn.

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 LITERATURE SURVEY
[2]A. P. Singh, A. Rai, A. Rajput, P. C. Joshi and A. Prakash, "Design and
Analysis of High Speed RISC Processor Using Pipelining Technique," 2022
4th International Conference on Advances in Computing, Communication
Control and Networking (ICAC3N), Greater Noida, India, 2022.
 The RISC processor consists of key components such as ALU (Arithmetic
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Logic Unit), Controller, Register files, and Data memory unit.

 The processor follows the von Neumann architecture, which utilizes a single
shared memory for both instructions and data.
 The design aims to be simple and clean, providing ease of investigation.
 The processor incorporates 15 instructions in its instruction set.
 Logical verification of the design is performed using Modelsim.
 RISC processors have hardwired instruction sets that enable faster instruction
execution. Instructions are typically one word in length, and microcodes are
not required for single-cycle execution.

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 LITERATURE SURVEY
[3] .Mohammad Zaid, Prof. Pervez Mustajab” DESIGN AND
APPLICATION OF RISC PROCESSOR” 2017 International Conference on
Multimedia, Signal Processing and Communication Technologies
(IMPACT),Nov 2017
 The processor is capable of executing a higher number of instructions due to
its simple design and reduced critical path delay.
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 The aim of the design is to improve performance and increase the speed of
operation.
 The multi-cycle approach allows for a more detailed and controlled execution
of instructions, which can result in improved performance.
 The design of the processor aims to strike a balance between performance,
simplicity, and critical path delay, optimizing overall system efficiency.

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 LITERATURE SURVEY
[4]. Galani Tina G., Riya Saini and R.D.Daruwala”Design and
Implementation of 32 – bit RISC Processor using Xilinx” International
Journal of Emerging Trends in Electrical and Electronics (IJETEE – ISSN:
2320-9569) Vol. 5, Issue. 1, July-2013.
 The RISC processor architecture consists of components such as the
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Arithmetic Logic Unit (ALU), Control Unit (CU), Barrel Shifter, Booth's
Multiplier, Register File, and Accumulator.
 The processor follows a load/store (Von Neumann) architecture, where all
operations are performed on operands held in registers, and the main memory
is accessed through load and store instructions.
 The processor employs a five-stage pipeline, including Instruction Fetch (IF),
Instruction Decode (ID), Execution (EX), Data Memory (MEM), and Write
Back (WB) stages.
 The ALU performs arithmetic and logical operations, while the Barrel Shifter
and Booth's Multiplier handle rotation and multiplication operations,
respectively.

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 GAP ANALYSIS AND OUTCOME OF
LITERATURE SURVEY

1. In ref[1] they designed 8-bit ALU, I/O ports, registers, flag register.
Implemented pipelining, Harvard architecture, 29 simple instructions.
Tested, optimized, understood trade-offs for a functional processor.
Drawback of them is it can only work up to 8 bit and limited to 29
instructions.
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2. In ref[2] the RISC processor uses von Neumann architecture with shared
memory, featuring ALU, Controller, Register files, and Data memory. It
emphasizes simplicity, with 15 instructions in its set, verified using
Modelsim, and gains speed from hardwired instruction sets for single-
cycle execution. Drawback of this is it can only work upto 16 bit and it
uses von Neumann architecture.
3. In ref[3] the processor executes more instructions with a simple design
and reduced critical path delay, improving performance and speed. Multi-
cycle approach enhances controlled execution for better performance.
Aim is to balance performance, simplicity, and critical path delay,
optimizing system efficiency.Drawback of this instruction set is less
optimized.

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 GAP ANALYSIS AND OUTCOME OF
LITERATURE SURVEY

4. In ref[4] RISC processor components: ALU, CU, Barrel Shifter, Booth's

Multiplier, Register File, and Accumulator. Follows load/store (Von
Neumann) architecture. Drawback of this is, usage of Von Neumann
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architecture.
5. To overcome all the drawbacks mentioned above, We are implementing 32-
bit RISC processor with Harvard architecture and highly optimized
Instruction Set.

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 GAP ANALYSIS AND OUTCOME OF
LITERATURE SURVEY
• R-type, I-type and J-type are the 3 types of instructions we are using in this
RISC processor.
• ISA format for R-type instructions is

Opcode rs1 rs2 rd Shftamnt Function

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(6 bits) (5 bits) (5 bits) (5 bits) (5 bits) (6 bits)

• Actual ISA format for I-type instruction is

Opcode rs rd Immediate/Offset
(6 bits) (5 (5 bits (16 bits)
bits)
• And J-type format is

Opcode Target address

(6 bit) (26 bits)

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 GAP ANALYSIS AND OUTCOME OF
LITERATURE SURVEY

• Optimized ISA format for I-type format is:

Opcode rs rd Imm Immediate/Offset
(5 bits) (5 bits) (5 bits) (1 bit) (16 bits)
modified Instruction Set Architecture
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• Instead of using 6 bit Opcode here we are using 5 bits Opcode and 1 bit
imm.
Advantages of modified ISA:
• Opcode decoding is much faster than the earlier proposed methodology.
• No need to decode the complete Offset, if there is immediate address in the
instruction, then imm is set to 1, else imm set to 0.
• Hence performance and speed of the processor increases.

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 BLOCK DIAGRAM
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Block Diagram of RISC Processor

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 PROPOSED METHODOLOGY/ ALGORITHM
The proposed methodology is as follows:-

Step 1. Conduct a literature review.

Step 2. Analysing RISC Architecture.
Step 3. Studying Instruction Set Architecture .
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Step 4. Design the Instruction Fetch Unit.

Step 5. Design the Instruction Decode Unit.
Step 6. Design the Execution Unit.
Step 7 . Design the Control Unit.
Step 8. Design the Memory Interface.
Step 9. Integrate the Modules.
Step 10. Implement the Modules in Verilog
Step 11. Synthesize and Implement.
Step 12.Testing and Validate.

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 Gant Chart

By 15-07-2023: Literature survey.

By 29-07-2023: Methodology Implementation.

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By 26-08-2023: Methodology Implementation.

By 16-09-2023: Validation of Results.

By 07-10-2023: Documentation.

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 References
1. Jikku Jeemon “Low Power Pipelined 8-bit RISC Processor Design and
Implementation on FPGA”International Conference on Control,
Instrumentation, Communication and Computational Technologies ,2015.
2. A. P. Singh, A. Rai, A. Rajput, P. C. Joshi and A. Prakash, "Design and
Analysis of High Speed RISC Processor Using Pipelining Technique," 2022
4th International Conference on Advances in Computing, Communication
GMR Institute of Technology

Control and Networking (ICAC3N), Greater Noida, India, 2022.

3. Mohammad Zaid, Prof. Pervez Mustajab” DESIGN AND APPLICATION OF
RISC PROCESSOR” 2017 International Conference on Multimedia, Signal
Processing and Communication Technologies (IMPACT),Nov 2017
4. Galani Tina G., Riya Saini and R.D.Daruwala”Design and Implementation of
32 – bit RISC Processor using Xilinx” International Journal of Emerging
Trends in Electrical and Electronics (IJETEE – ISSN: 2320-9569) Vol. 5,
Issue. 1, July-2013.

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 GMR Institute of Technology

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