Progress Presentation

on
Efficient Hardware Implementations of Shadow Lightweight Block
Cipher for Resource Constraint Applications

Under Supervision of:

Presented by:
Dr. Bibhudendra Acharya
G.Krishna Pranav
Associate Professor 21266003
M.Tech 4th Sem
Department of Electronics and Communication Engineering
(VLSI Design and Embedded System)
National Institute of Technology, Raipur
08/10/2023 April 2023
Contents
 Introduction
 Literature Survey
 Problem Statement and Motivation
 Research Objectives and Methodolgy
 Algorithm of Shadow lightweight Block Cipher
 Work done to fulfill objectives
• Chapter 3: Optimized Hardware Implementation of Iteration Architecture and Encryption &
Decryption Architectures of Shadow Lightweight Block Cipher
• Chapter 4: Hardware Implementations of High Frequency Pipelined Architecture and High
Throughput Unrolled Architectures of Shadow Lightweight Block Cipher for Resource
Constraint Applications
• Chapter 5: Hardware Implementation of High efficiency Unified Architecture of Shadow Lightweight
Block Cipher
 Conclusion and Future Work
 Dissemination
 References Presented by Krishna Pranav, National 2
Institute of Technology, Raipur (Dept of ECE)
08/10/2023
 Introduction
• Internet is a boon to the mankind which is involved in every aspect of our life and connects every nook and.corner
of the world.
• The Internet of Things (IoT) has been named "the next industrial revolution" due to the way it will change the
way humans live, work, engage, and travel, and how organizations and governments cooperate with the world.
• We use IoT devices for enabling new solutions for various issues related to diverse fields like personal, housing,
industry, medical, automotive, communication etc.
• A major challenge in the IoT era is with the increase in the number of devices comes the issue of data security and
data integrity.
• Cryptography is the process of converting plain text information into ciphertext. With the help of a unique key,
encryption and decryption of data can be performed for secured communication
• The term is derived from the Greek word kryptos, which means hidden.

• Ciphers are the tools which convert plain text to encrypted text.

08/10/2023 Presented by Krishna Pranav, National 3

Institute of Technology, Raipur (Dept of ECE)
 Cryptography
• Cryptography is the process of converting plain text information into ciphertext.
• With the help of a unique key, encryption and decryption of data can be performed for secured
communication. Confidentiality, Non-repudiation, Integrity and Authenticity are the four objectives of
Cryptography.
• Conventional cryptography examples: Servers and Desktops; Tablets and Smart phones.

Cryptography

Symmetric Asymmetric
Key Key Hashing
Cryptography Cryptography

Figure 1.1: Types of Cryptography

08/10/2023 Presented by Krishna Pranav, National 4

Institute of Technology, Raipur (Dept of ECE)
 Types of Cryptography
Symmetric Cryptography Asymmetric Cryptography
• Requires same key for encryption and • Uses 2 different keys for encryption and
decryption decryption
• Simple and fast • More secured
• Less complex • Relatively Complex
• Less secured

Figure 1.2: Symmetric Key Cryptography [64] Figure 1.3: Asymmetric Key Cryptography [64]
08/10/2023 Presented by Krishna Pranav, National 5
Institute of Technology, Raipur (Dept of ECE)
Contd...
Hash functions:
• It performs encrypting the message by converting a given string into a fixed length string.
• The hashing algorithms produce different outputs for each input given.
• The only method to crack a hash is to keep trying every potential input until the same hash is
obtained.
• A hash can be used for hashing data (such as passwords) and in certificates.
• Some of the examples are MD5, SHA-1, SHA-2 family.

08/10/2023 Presented by Krishna Pranav, National 6

Institute of Technology, Raipur (Dept of ECE)
 Block Ciphers and Stream Ciphers

Block Ciphers Stream Ciphers

The conversion of the plaintext to ciphertext is performed Stream ciphers are also symmetric key ciphers which
by dividing the plaintext into blocks of data and performs the process of encryption on a plaintext by
operating on one block at a time. operating on byte of data at a time.

Block cipher uses either 64 bits or more than 64 bits. While stream cipher uses 8 bits.

Block Ciphers are simple Stream Ciphers are complex

Block cipher Uses confusion as well as diffusion. While stream cipher uses only confusion

Examples of block ciphers are AES, DES, TEA, QTL, Some of the examples of the lightweight stream ciphers
LILLIPUT etc. are RC4, FISH, SEAL, Helix etc.

08/10/2023 Presented by Krishna Pranav, National 7

Institute of Technology, Raipur (Dept of ECE)
Design Strategies
SPN based Network Feistel Network
SPN-based networks use substitution and permutation Feistel Ciphers are straightforward to decipher because of
boxes, or Pboxes and Sboxes, to convert plain text their simple designs.
into Cipher text.

These boxes strengthen the security of the underlying The two phases of a Feistel network's encryption and
cryptographic technique by adding levels of decryption are quite identical, with the only difference being
uncertainty and diffusion. the scheduling of the network's keys.

Lightweight SPN network block cryptography is Lightweight Feistel network block cryptography is shown in
shown in Figure 5. Figure 5.

Examples – PRESENT, Klein, RECTANGLE, LED, Examples - Piccolo, LILLIPUT, QTL, SEA, TWINE,
PRINCE, PRINT, mCrypton LBlock

08/10/2023 Presented by Krishna Pranav, National 8

Institute of Technology, Raipur (Dept of ECE)
 Design Strategies

Figure 1.4: Feistel Network [65] Figure 1.5: Substitution-Permutation Network [36]
08/10/2023 Presented by Krishna Pranav, National 9
Institute of Technology, Raipur (Dept of ECE)
 Applications of Cryptography

• E-Commerce
• Business Transaction
• Data Security
• Internet Payment System
• Defense Services
• Access Control

08/10/2023 Presented by Krishna Pranav, National 10

Institute of Technology, Raipur (Dept of ECE)
 Conventional Cryptography Challenges in IoT Devices

Figure 1.6: Conventional Cryptography Challenges in IoT Devices [69]

08/10/2023 Presented by Krishna Pranav, National 11
Institute of Technology, Raipur (Dept of ECE)
 Introduction of Lightweight Cryptography
• Lightweight Cryptography aims at the development of algorithms for constrained devices.

• Here, basic constrains are Memory, Power, and Size.

• Lightweight ciphers have been proposed to provide strong security at a lower cost and lesser
power consumption than standard solutions.

• Radio Frequency Identification tags (RFID), IoT devices, and Wireless Sensor Network (WSN)
are some typical examples, which utilize lightweight cryptography.

08/10/2023 Presented by Krishna Pranav, National 12

Institute of Technology, Raipur (Dept of ECE)
 Architectural Strategies
 Round Based Architecture
– One round function of a block cipher or a stream cipher is processed in a single clock cycle.
– By using a round based strategy, low area and power consumption can be achieved in a design at
the expense of high throughput generation.
 Pipelined Architecture
– To increase the frequency, we use a register in the middle of the critical route.
– When a register is placed in the middle of the critical path, the resulting critical path length is
reduced which results in a faster clock rate and high frequency.
 Parallel or Loop Unrolled Architecture
– Multiple Rounds are preformed in a single clock cycle.
– These kind of implementations generate high throughput output at the expense of increased area
occupancy and power consumption.
 Unified Architecture
– This is an architecture strategy where we combine different versions of the cipher into a single
structure to increase the flexibility and usability.

08/10/2023 Presented by Krishna Pranav, National 13

Institute of Technology, Raipur (Dept of ECE)
 Applications of Lightweight Cryptography

Figure 1.7: Applications of Lightweight Cryptography [70]

08/10/2023 Presented by Krishna Pranav, National 14
Institute of Technology, Raipur (Dept of ECE)
 Literature Survey
Sr. Title of the Paper Author Description Published In
no.
1. FPGA Implementation N. Shrivastava • In the paper, authors have proposed different hardware implementations of International Journal
of RECTANGLE Block and B. Acharya RECTANGLE LWC namely, Iterative design, 16-bits architecture, RAM-based of Innovative
Cipher Architectures design, Reduced Substitution box design and Iterative design with partial loop Technology and
[24] unrolled. Exploring
• The presented designs focus on improving the overall security in low resource Engineering, 2019.
environments.
2. VLSI Implementation A. Nigar and B. • Authors have presented an implementation of LiCi block cipher using three International
of LiCi Cipher [4] Acharya different architectures namely serialized, reduced datapath and pipelined on Journal of Innovative
different FPGA platforms. Technology and
• The reduced datapath architecture consumes the least dynamic power. The Exploring
throughput obtained for serialized architecture is less as compared to the reduced Engineering
datapath and pipelined architectures. (IJITEE), 2019
• In the paper, the authors also suggested efficient ways of improving the results,
by using the resources of FPGA like SRL16, BRAM and RAM/ROM
implementation.
3. An FPGA-Based J. Elbirt, W. Yip, • Reprogrammable devices such as FPGAs are highly attractive options for IEEE Transactions
Performance Evaluation B. hardware implementations of encryption algorithms On Very Large Scale
of the AES Block Cipher Chetwynd, and C. • Multiple architectural implementation options can be explored for each Integration (VLSI)
Candidate Algorithm Paar • algorithm. Systems, 2001
Finalists [31] • A strong focus was to achieve high-throughput implementations.
4. AES Datapath D. H. Bui, D., • In this paper, hardware architecture of AES is optimized for high-speed ultralow- IEEE Transactions
Optimization Strategies Puschini, S., power ultralow-energy IoT applications with multiple levels of security. on Very Large Scale
for Low-Power Low Bacles-Min, E., • Design supports multiple security levels through different key sizes, power and Integration (VLSI)
Energy Multi security Beigné, and X.T. energy optimization. Systems, 2017
Level Internet-of-Things • Achieved an energy per bit comparable with the lightweight standardized
Applications [34] algorithm PRESENT of less than 1 pJ/b at 10 MHz at 0.6 V with throughput of
08/10/2023 28 Mb/s.
Presented by Krishna Pranav, National
Institute of Technology, Raipur (Dept of ECE)
15
 Literature Survey
Sr. Title of the Paper Author Description Published In
no.
5. Energy-Efficient and High- P. Singh, P. Modi, B. • Energy and Throughput efficient architectures of KLEIN International Journal
throughput Implementations of Acharya, R. K. cipher are presented in the paper. of Innovative
Lightweight Block Cipher [54] Chaurasiya • The authors implemented the cipher using two different Technology and
design technique styles namely pipelined based and multi- Exploring Engineering
round based. (IJITEE), 2019
• With the pipelined technique optimization is observed with
respect to the throughput achieved.
• With the multi-round technique, energy and throughput
efficient results are obtained making the architecture
suitable for high speed applications.

6. IP Design of Corrected Block H. Yeo, S. Sonh and M. • In this paper round-based architecture of XXTEA KSII Transactions on
TEA Cipher with Variable- Kang lightweight block cipher design is presented which works Internet and
Length Message for Smart IoT on variable length block size messages. Information Systems,
[3] • Aim of this design was to minimize hardware resource 2020
usage and maximize throughput.
 
 
7. High throughput and low Z. Mishra and B. • In the paper, pipelined and serial architectures of secure Journal of Information
area architecture of secure IoT Acharya IoT (SIT) algorithm for encryption are proposed for Security and
algorithm for medical image obtaining high speed and low area respectively. Applications, 2020.
encryption [6] • In the work, authors have performed medical image
encryption and performed security analysis.

8. Lightweight Hardware C. A. Lara-Nino,A. • In this paper, two new architectures based on key IEEE Transactions
Architectures for the Diaz-Perez and M. generation mechanism has been proposed. on circuits and
PRESENT Cipher in FPGA Morales_x0002_Sandova • Analysis of resource usage is done on proposed algorithm systems,
[62]
08/10/2023 l and 3Pranav,
Presented by Krishna state-of-art algorithm
National September, 2017
• Spartan3,
Institute of Technology, RaipurVirtex4 FPGA
(Dept of ECE) devices are used to study the
16
 Literature Survey
Sr. no. Title of the Paper Author Description Published In
9. Efficient hardware N. Shrivastava, P. Singh, • The authors presented three different architectures for International Journal
implementations of QTL cipher B. Acharya implementing QTL block cipher. of High Performance
for RFID applications [19] • The reduced datapath, pipelined and unified Systems Architecture,
architectures focused on obtaining area utilization, 2020.
improved operating frequency and flexible security
respectively.
• In this work, the authors have provided an option of
choosing the level of security of the design by
incorporating different key scheduling structures in the
architecture.
10. Performance optimised G. Ramu, Z. Mishra, P. • FPGA implementation of the ultra lightweight block International Journal of
architectures of Piccolo block Singh and B. Acharya cipher Piccolo is presented in this paper. High Performance
cipher for low resource IoT • For optimization of the design, three different Systems Architecture,
applications[26] architectures are described namely loop rolled, parallel 2020.
round based and pipelined architectures.
• The presented work is implemented on various FPGA
devices. The authors have shown that the design
obtained low area and high throughput which makes it a
suitable choice for low resource devices.
11. Efficient hardware Z. Mishra, and B. • Authors in this paper have designed round-based International Journal
implementation of TEA, XTEA Acharya architectures of TEA, XTEA and XXTEA for low of High Performance
and XXTEA lightweight ciphers resource applications. Systems Architecture,
for low resource IoT • The designed architectures achieved less area and 2021.
applications [42] dynamic power consumption making it suitable for
RFID applications.
• The hardware implementation of the work is performed
on various FPGA device families.
08/10/2023 • DuePranav,
Presented by Krishna to theNational
use of round-based architecture, area 17
optimization is observed
Institute of Technology, Raipur (Dept of ECE) in the results obtained.
 Literature Survey
Sr. Title of the Paper Author Description Published In
no.
12. High throughput novel Z. Mishra and B. • Pipelined architecture of TEA Family Block Cipher is Journal of Information
architectures of TEA family for Acharya presented in this paper. Security and
high speed IoT and RFID • A hybrid architecture which imitates all three lightweight Applications, 2021
applications [1] ciphers (TEA, XTEA and XXTEA) is also proposed
which provides efficient ultra-high throughput at the
 
expense of area utilization.
 
13. Effective hardware P. Modi, P. Singh, and B. • In this paper, the authors proposed three different International Journal of
architectures for LED and Acharya hardware architectures based on LED and PRESENT High Performance
PRESENT ciphers for resource- ciphers. Round based and serial based design techniques Systems Architecture,
constrained applications [43] are used for implementation. 2021.
• High performance results are achieved.
• The implementation of the designs are performed on
various FPGA device families.
14. FPGA implementation of M. N. Hasan, M. T. • This paper presents a hardware implementation of 3rd International
LBlock lightweight block cipher Hasan, R. N. Toma and M. LBlock cipher on Altera DE1 FPGA board. Conference on
[46] Maniruzzaman • The implementation results shows better throughput and Electrical Engineering
the results are compared to XTEA, Hummingbird and and Information
KATAN ciphers. Communication
Technology (ICEEICT),
2016
15. An Advanced Symmetric Block C. U. Bhaskar and C. • This paper presents technique to enhance security of Innovations in Power
Cipher based on Chaotic Systems Rupa XXTEA cipher with the help of a chaotic system. and Advanced
[7] • Both text and image files are used as data. Computing
Technologies (i-PACT),
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Institute of Technology, Raipur (Dept of ECE)
 Literature Survey
Sr. Title of the Paper Author Description Published In
no.
16. Hardware Implementation of a P. Israsena and S. • This paper presents implementation of three different RFID Security,
TEA-Based Lightweight Wongnamkum architectures namely parallel, sequential and digit-serial Springer, Boston,
Encryption for RFID Security [8] architectures. MA, 2008
• This paper focusses on providing solutions for low-cost
secure RFID based on TEA encryption.
• The effectiveness of TEA architecture is evaluated by
providing a comparison between TEA and AES cipher in
terms of performance.
17.  Chai-Tea, Cryptographic JP. Kaps • In this paper a novel architecture of XTEA cipher is 9th International
Hardware Implementations of implemented for ultra-low power applications such as RFID Conference on
xTEA [10] tags and wireless sensor nodes. Cryptology in India,
• Pipelined Architecture is implemented on FPGA and ASIC 2008
platform.
18.  Cryptanalysis of XXTEA [12] E. Yarrkov • This paper presents security attack analysis of XXTEA. International
• Differential cryptanalysis technique is used. Association for
Cryptologic
Research
(IACR), 2010
19. LBlock: A Lightweight Block W. Wu, L. Zhang • In this paper, the authors have performed hardware Springer, Berlin,
Cipher [47] implementation of LBlock cipher on 0.18µm CMOS Heidelberg, 2011.
technology.
• A security evaluation is also done in order to study the
response against various known attacks.
• A software implementation is also presented on a 8-bit
microcontroller.
08/10/2023 Presented by Krishna Pranav, National 19
Institute of Technology, Raipur (Dept of ECE)
 Literature Review
S.No. Title of the paper Author Description Published in
1 Shadow: A Lightweight Ying Guo, Lang Li, • Round function and Key Function IEEE Internet of
Block Cipher for IoT Botao Liu • Encryption and decryption of shadow Cipher Things journal, Vol.
Nodes [3] • Different Architectures of the Cipher 8, no. 16 (2021)
• Hardware Implementation using FPGA
• Performed Security Analysis

2 High throughput and low Z. Mishra and B. • In the paper, pipelined and serial architectures of Journal of
area architecture of secure Acharya secure IoT (SIT) algorithm for encryption are Information Security
IoT algorithm for medical proposed for obtaining high speed and low area and Applications.
image encryption [4] respectively. (2020)
• In the work, authors have performed medical
image encryption and performed security
analysis.
3 Lightweight Cryptography Panasayya Yalla, and • Reprogrammable devices such as FPGAs are International
for FPGA [16] Jens-Peter Kaps highly attractive options for hardware Conference on
implementations of encryption algorithms. Reconfigurable
• Multiple architectural implementation options Computing and
are explored for each algorithm. A strong focus FPGAs, IEEE, 2009
is placed on high-throughput implementations.

Thursday, August 10, 2023 Presented by Krishna Pranav, National 20

Institute of Technology, Raipur (Dept of ECE)
 Literature Review
S.No. Title of the paper Author Description Published in
4 Advanced lightweight Saurabh Singh, • The challenges and solutions of Springer (2017)
encryption algorithms for Pradip Kumar encryption algorithms
IoT devices: survey, Sharma, Seo Yeon • light weight primitives
challenges and solutions Moon, Jong Hyuk • Security architecture in IOT
[17] Park et al
5 Lightweight Cryptography Thakor Vishal a, • Basics of light weight IEEE Access, Vol 9
Algorithms for Resource Mohammad Abdur Cryptography (2021)
Constrained IoT Devices: Razzaque and • Hardware and software metrics of
A Review, Comparison Muhammad r. A. performance
and Research Khandaker • Key challenges of conventional
Opportunities [18] cryptography
• Different ciphers based on Feistal,
SPN , Generalised fiestal network
and ARX are studied
6 High Throughput Compact Zeesha Mishra, • high throughput architecture of Proceedings of the
Area Architecture of Bibhudendra XXTEA-128 cipher using 52nd Annual
XXTEA for IoT Acharya pipelining technique Design Automation
application [16] • Designing of a controller Conference on -
DAC ’15, 2015

Thursday, August 10, 2023 Presented by Krishna Pranav, National 21

Institute of Technology, Raipur (Dept of ECE)
 Shadow Cipher
• Shadow is a cipher which has a combination of ARX operations and the generalized Feistel
structure consists of four branches, the encrypted outputs of which are concatenated to
generate the cipher text.
• It has 2 versions of its own, They are Shadow-32 and Shadow-64.
• If the algorithms processes an input block of 32 bits along with a 64-bit key, iterating for 16
rounds to generate 32 bit output, It is termed as Shadow-32.
• Similarly, If a block size of 64 bits with a 128-bit key, with round number, i.e., RN of 32,
results in 64 bit output, which is called Shadow-64.

Thursday, August 10, 2023 Presented by Krishna Pranav, National 22

Institute of Technology, Raipur (Dept of ECE)
 Shadow Algorithm
Input: Plaintext - 32 bit , Primary key - 64 bit
Output: Ciphertext – 32 bit
•(L0, L1, R0, R1) Plaintext;
•for i=1 to 16 do
s0=(L0⋘1&L0⋘7)⨁L1⨁L0⋘2⨁keyi0;
s1=(R0⋘1&R0⋘7)⨁R1⨁R0⋘2⨁keyi1;
L0'=s1;
L1'=(s0⋘1&s0⋘7)⨁L0⨁s0⋘2⨁keyi2;
R0'=s0;
R1'=(s1⋘1&s1⋘7)⨁R0⨁s1⋘2⨁keyi3;
•end for
•Ciphertext  (L0’, L1’, R0’, R1’);
•Return Ciphertext;

Thursday, August 10, 2023 Presented by Krishna Pranav, National 23

Institute of Technology, Raipur (Dept of ECE)
 Basic Round Function of Shadow Algorithm

• The basic round function of Shadow-32 is as shown in the fig below which performs ARX operations.

Fig 1.8: Shadow 2-branch Round Function

Thursday, August 10, 2023 Presented by Krishna Pranav, National 24

Institute of Technology, Raipur (Dept of ECE)
Contd.. L0 L1 R0 R1

<<<1 + <<<1 +

<<<7 <<<7
& + & +
<<<2 <<<2

FIRST ROUND
Key-1 + Key-2 +

<<<1 + <<<1 +

<<<7 <<<7
& + & +
<<<2 <<<2

Key-3 + Key-4 +

<<<1 + <<<1 +

<<<7 <<<7
& + & +
<<<2 <<<2

Key-1 + Key-2 +

<<<1 + <<<1 +

<<<7 <<<7
& + & +
<<<2 <<<2

Key-3 + Key-4 +

SHADOW ROUND FUNCTION

Thursday, August 10, 2023 25
Fig 1.9: Complete Round Function of Shadow Algorithm
Presented by Krishna Pranav, National Institute of Technology, Raipur (Dept of ECE)
 Problem Statement and Motivation
• From the past few years, the Conventional cryptographic algorithms such as Data Encryption
Standard (DES), Triple DES (3DES), Advanced Encryption Standard (AES), Rivest-Shamir-
Adleman (RSA), etc., have been used for secure data encryption.
• Conventional cryptographic algorithms do not perform well in resource constrained environments
due to their higher block and key sizes, energy consumptions.
• Lightweight cryptography is designed for optimal performance in resource constrained
environments such as IoT sensor nodes and RFID tags.
• It aims to use less storage capacity, computing power and power consumption to provide security in
such applications. This standard is quite and simple as compared to conventional techniques and less
secure.
• In order to enhance the performance of ciphers in hardware, different implementation techniques of
SHADOW cipher are proposed.
• This motivated for the designing of various architectures for obtaining optimized results for
performance, Throughput, area, power consumption and energy utilization.

08/10/2023 Presented by Krishna Pranav, National 26

Institute of Technology, Raipur (Dept of ECE)
 Research Objectives
Objective 1:
 To design hardware architecture of Shadow lightweight block cipher using Iteration implementation for a 32-bit block
size to achieve reduction in area.
 To design hardware architecture of Encryption and Decryption algorithms of 32-bit input block size Shadow lightweight
block cipher to verify its operation and its functionality.
Objective 2:
 To design hardware architecture of Shadow lightweight block cipher using Pipelined implementation for a 32-bit input
Shadow lightweight block cipher to achieve increase in frequency.
 To design hardware architecture of Shadow lightweight block cipher using 8-Clock Unrolled implementation for a 32-bit
input Shadow lightweight block cipher to achieve increase in throughput.
 To design hardware architecture of Shadow lightweight block cipher using 4-Clock Unrolled implementation for a 32-bit
input Shadow lightweight block cipher to achieve increase in throughput.
 To design hardware architecture of Shadow lightweight block cipher using 2-Clock Unrolled implementation for a 32-bit
input Shadow lightweight block cipher to achieve increase in throughput.
Objective 3:
 To design hardware architecture of Shadow lightweight block cipher using Unified implementation for a 32/64-bit block
size to achieve better efficiency and for Resource Constraint applications.

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Institute of Technology, Raipur (Dept of ECE)
 Methodology
• The functionality of the design is checked by performing simulation on Xilinx ISE 14.7 and Xilinx
Vivado Design Suite.
• FPGA implementation of the architectures are performed using Xilinx ISE Design Suite on different
FPGA device families namely Spartan-6, Virtex-5, Virtex-7.
• The reports obtained for the implementations has device utilization summary which describes the
amount of Slices, LUTS and registers being occupied and estimation of maximum operating
frequency is provided

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Institute of Technology, Raipur (Dept of ECE)
 Chapter - 3
Optimized Hardware Implementation of Iteration
Architecture and Encryption & Decryption
Architectures of Shadow Lightweight Block Cipher

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Institute of Technology, Raipur (Dept of ECE)
 Chapter 3
Optimized Hardware Implementation of Iteration Architecture and
Encryption & Decryption Architectures of Shadow Lightweight Block
Cipher
Introduction:
 Chapter 3 describes the hardware implementations of Round based and Encryption and decryption
design techniques of Shadow-32 Lightweight block cipher.
 In the Round-based architecture, The algorithm requires single clock cycle to complete the encryption
process and get encrypted output which is also known as ciphertext.
 Round based Architecture is also known as Iteration Architecture.
 The Proposed Architecture of Iteration Algorithm are as shown in the figure below

08/10/2023 Presented by Krishna Pranav, National 30

Institute of Technology, Raipur (Dept of ECE)
 3(a) Proposed Round Based Architecture

Fig.9: Proposed Hardware for Round based Architecture of Shadow Lightweight Block Cipher
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Presented by Krishna Pranav, National Institute of Technology, Raipur (Dept of ECE)
Results of Round Based Architecture
Table 1 : Results of Round based Architecture on Various boards
XC5VLX50T XC7VX330T XC6SLX4
 Parameter/Device
FF1136 -2 FFG1157 -3 TQG144 -3
Virtex 5 Virtex 7 Spartan 6
LUT 136 136 138
FFs 100 100 100
Slices 101 102 104
Max. Frequency (MHz) 531.194 827.952 334.358
Cycle 17 17 17
Throughput 999.894 1558.497 629.379

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Institute of Technology, Raipur (Dept of ECE)
3(b) Encryption and Decryption Process

• The Encryption and Decryption of the Shadow-32 Algorithm is performed to check the
functionality of the implemented algorithm.
• For the encryption, we need a round function and a key module, which combine together and
results in Encrypted output.
• We check the functionality by verifying the output of decryption with the input of
encryption.
• The round function iterates for 16 rounds while coordinating with key module which
generates key for each and every round to generate the encrypted output.
• The Proposed Architecture of Encryption and Decryption are as shown in the figure below

08/10/2023 Presented by Krishna Pranav, National 33

Institute of Technology, Raipur (Dept of ECE)
Proposed Encryption and Decryption Architectures
Plain Cipher
Text Text

K
Key
ROUND 1
1,2,3,4 E ROUND 1
Y
Key
ROUND 2 G ROUND 2
5,6,7,8
E
N
U

E
R
A
T
ROUND Key O Key ROUND
16 61,62,63,64 R 1,2,3,4 16

Cipher Plain
Text Text

ENCRYPTION AND DECRYPTION

Fig : Proposed Encryption & Decryption Architectures

08/10/2023 Presented by Krishna Pranav, National 34
Institute of Technology, Raipur (Dept of ECE)
Encryption
The below figure shows the input applied for encryption process

08/10/2023 Presented by Krishna Pranav, National 35

Institute of Technology, Raipur (Dept of ECE)
Simulation results of Encryption & Decryption

Fig.10 :Simulation results of Encryption

08/10/2023 Presented by Krishna Pranav, National 36

Institute of Technology, Raipur (Dept of ECE)
Decryption
• The below figure shows the input applied for encryption process

08/10/2023 Presented by Krishna Pranav, National 37

Institute of Technology, Raipur (Dept of ECE)
Simulation results of Decryption

Fig.10 :Simulation Results of Decryption

08/10/2023 Presented by Krishna Pranav, National 38

Institute of Technology, Raipur (Dept of ECE)
 Chapter 4
Hardware Implementations of High Frequency Pipelined
Architecture and High Throughput Unrolled Architectures of
Shadow Lightweight Block Cipher for Resource Constraint
Applications

08/10/2023 Presented by Krishna Pranav, National 39

Institute of Technology, Raipur (Dept of ECE)
4(a): Proposed Pipelined Architecture
KEY MODULE
IN[32:25] IN[24:17]
Key-in IN[16:9] IN[8:1]

1
MUX
MUX MUX
MUX MUX
KEY IN
Reg 1 Reg 2 REG KEY-0 Reg 3 Reg 4

<<<1 <<<1
+ NX
MODULE
ADD
ROUND
CONSTANT
NX
MODULE
ADD
ROUND +
<<<7 CONSTANT
<<<7

<<<2 + PERMUTATION PERMUTATION

+ <<<2

+ KEY-0 KEY-1 +

KEY-1 KEY-2

<<<1 <<<1
+ NX
MODULE
ADD
ROUND
NX
MODULE
ADD
ROUND +
<<<7 CONSTANT CONSTANT
<<<7

<<<2 + PERMUTATION PERMUTATION

+ <<<2

+ KEY-2 KEY-3 +
Reg A Reg B Reg C Reg D
PIPELINE REGISTERS

Fig.10 : Proposed Pipelined Architecture

08/10/2023 Presented by Krishna Pranav, National 40

Institute of Technology, Raipur (Dept of ECE)
Results of Proposed Pipelined Architecture

Table 2 : Results of Pipelined Architecture on Various boards

XC5VLX50T XC7VX330T XC6SLX4
 Parameter/Device
FF1136 -2 FFG1157 -3 TQG144 -3
Virtex 5 Virtex 7 Spartan 6
LUT 172 189 189
FFs 132 134 145
Max Frequency (MHz) 495.417 728.173 312.402
Cycle 17 17 17
Throughput ( Mbps) 931.384 1368.965 587.315

08/10/2023 Presented by Krishna Pranav, National 41

Institute of Technology, Raipur (Dept of ECE)
4(b): Proposed 8-Clock Unrolled Architecture
Data Key
Input Input

1
MUX MUX

REG REG
1 2

ROUND Key KEY

FUNCTION 1,2,3,4 GENERATOR

ROUND Key KEY

FUNCTION 5,6,7,8 GENERATOR

8-CLOCK UNROLLED ARCHITECTURE

Fig.12 :Proposed 8-Clock Unrolled Architecture
08/10/2023 Presented by Krishna Pranav, National 42
Institute of Technology, Raipur (Dept of ECE)
Results of Proposed 8-Clock Unrolled Architecture

Table 2 : Results of Proposed 8-Clock Unrolled Architecture on Various boards

XC5VLX50T XC7VX330T XC6SLX4
 Parameter/Device
FF1136 -2 FFG1157 -3 TQG144 -3
Virtex 5 Virtex 7 Spartan 6
LUT 230 249 365

FFs 100 100 107

Max Frequency (MHz) 362.753 636.173 237.225
Cycle 17 17 17
Throughput ( Mbps) 1071.449 1496.079 614.854

08/10/2023 Presented by Krishna Pranav, National 43

Institute of Technology, Raipur (Dept of ECE)
4(c): Proposed 4-Clock Unrolled Architecture
Key Input Data Input

0
1
0
MUX MUX

REG 1 REG 2

Key
ROUND 1
1-4 K
E
Y
Key
ROUND 2 5-8 G
E
N
Key
E
ROUND 3 9-12 R
A
T
Key O
ROUND 4
13-16 R

4-CLOCK UNROLLED ARCHITECTURE

08/10/2023 Fig.12 :Proposed 4-Clock Unrolled Architecture 44

Presented by Krishna Pranav, National Institute of Technology, Raipur (Dept of ECE)
Results of Proposed 4-Clock Unrolled Architecture

Table 2 : Results of Proposed 4-Clock Unrolled Architecture on Various boards

XC5VLX50T XC7VX330T XC6SLX4
 Parameter/Device
FF1136 -2 FFG1157 -3 TQG144 -3
Virtex 5 Virtex 7 Spartan 6
LUT 304 458 405
FFs 98 98 98
Max Frequency (MHz) 172.973 263.421 108.038
Cycle 5 5 5
Throughput ( Mbps) 1107.03 1685.89 691.443

08/10/2023 Presented by Krishna Pranav, National 45

Institute of Technology, Raipur (Dept of ECE)
4(d): Proposed 2-Clock Unrolled Architecture
Key Data
Input Input
0

1
1

0
MUX MUX

REG 1 REG 2

Key
1-4 ROUND - 1

Key
ROUND - 2
5-8

Key

R ou n d3,4,5,6
Generator

Key
25-28
ROUND - 7

Key
29-32
ROUND - 8

2-CLOCK UNROLLED ARCHITECTURE

08/10/2023 Fig.12 :Proposed 2-Clock Unrolled Architecture 46

Presented by Krishna Pranav, National Institute of Technology, Raipur (Dept of ECE)
Results of Proposed 2-Clock Unrolled Architecture

Table 2 : Results of Proposed 2-Clock Unrolled Architecture on Various boards

XC5VLX50T XC7VX330T XC6SLX4
 Parameter/Device
FF1136 -2 FFG1157 -3 TQG144 -3
Virtex 5 Virtex 7 Spartan 6
LUT 303 303 303
FFs 98 98 98
Max Frequency (MHz) 98.892 115.937 61.943
Cycle 3 3 3
Throughput ( Mbps) 1054.19 1662.29 660.312

08/10/2023 Presented by Krishna Pranav, National 47

Institute of Technology, Raipur (Dept of ECE)
 Chapter 5:
Hardware Implementation of High Efficiency Unified
Architecture of Shadow Lightweight Block Cipher for
Resource Constrained Applications

08/10/2023 Presented by Krishna Pranav, National 48

Institute of Technology, Raipur (Dept of ECE)
Proposed Unified Architecture
For 128-bit Key inputs
Kin, k1, k2, k3

ADD
ROUND
NX
64 bit Input
CONSTANT
MODULE With
6
Constants
Round
Function
PERMUTATION

128 bit Key Outputs are

k1,k2,k3,k4

128 bit Key Generation SEL=1

2*1
MUX
SEL=0
For 64-bit Key inputs
Kin, k1, k2, k3

ADD
ROUND
SELECT
32 bit Input
NX CONSTANT
MODULE With
5 LINE
Constants Round
Function
PERMUTATION

64 bit Key Outputs are

k1,k2,k3,k4

64 bit Key Generation

UNIFIED ARCHITECTURE

Fig.15: Proposed Unified Architecture

08/10/2023 49
Presented by Krishna Pranav, National Institute of Technology, Raipur (Dept of ECE)
Results of Proposed Unified Architecture

Table 2 : Results of Proposed Unified Architecture on Various boards

XC5VLX50T XC7VX330T XC6SLX4
 Parameter/Device
FF1136 -2 FFG1157 -3 TQG144 -3
Virtex 5 Virtex 7 Spartan 6
LUT 495 505 511
FFs 257 257 261
Max Frequency (MHz) 390.518 416.675 172.058
Cycle 17/33 17/33 17/33
Throughput ( Mbps) 734.173/757.360 783.349/808.096 323.46/333.69

08/10/2023 Presented by Krishna Pranav, National 50

Institute of Technology, Raipur (Dept of ECE)
Simulation Results of Unified Architecture

Fig.: Simulation Results of Unified Architecture

08/10/2023 Presented by Krishna Pranav, National 51

Institute of Technology, Raipur (Dept of ECE)
Comparison Table
Through
Algorithm Slice LUT
put
LEA128/128 [28] 392 249 205.450
PRESENT64/128 [29] 88 283 316.120

PRESENT64/128 [29] 72 237 61.190

PRESENT64/128 [30] 73 239 203.190

SHADOW64/128 [5] 199 227 743.038
SHADOW32/64 [8-clk-Unrolled] 100 249 1071.449

SHADOW32/64 [4-clk-Unrolled] 98 304 1107.03

SHADOW32/64 [2-clk-Unrolled] 98 303 1054.19

Shadow 64/128 *[Round Based] 999.894
100 148
Shadow 64/128 *[Pipelined] 931.384
132 172
08/10/2023 52
 Algorithm Throughput (Mbps) Device
Contd. LEA-192 (Lee et al. 2014) 996 Virtex-5
LEA-256 (Lee et al. 2014) 505 Virtex-5
PRESENT 80 (Lara et al. 2017) 260.96 Virtex-5
LILLIPUT SP (Singh et al. 2019) 684.06 Virtex-5
LILLIPUT FP (Singh et al. 2019) 490.35 Virtex-5
PICCOLO UR (Ramu et al. 2020) 691.54 Virtex-5
PICCOLO RB (Ramu et al. 2020) 613.26 Virtex-5
Shadow 64/128 (Guo et al. 2021) 743.038 Virtex-5
SIT S (Mishra et al. 2020) 290.750 Virtex-5
SIMON 64/128 (Beaulieu et al. 2015) 870 Virtex-5
PRINCE (Kumar et al. 2023) 346.554 Virtex-5
RECTANGLE RB (Srivastava et al. 2019) 517.454 Virtex-5
RECTANGLE S (Srivastava et al. 2019) 206.107 Virtex-5
Shadow 64/128 *[8-clk unrolled] 1071.449 Virtex-5
Shadow 64/128 *[4-clk unrolled] 1107.03 Virtex-5
Shadow 64/128 *[2-clk unrolled] 1054.19 Virtex-5

08/10/2023 Shadow 64/128 *[Round Based] 999.894 Virtex-5 53

Shadow 64/128 *[Pipelined] 931.384 Virtex-5
 Results and Analysis
 The simulation and the performance analysis of the proposed architectures of Shadow family ciphers are performed
on Xilinx ISE 14.7 platform and the performance analysis is done on FPGA device using Xilinx Vivado tool. 
 FPGA are programmable integrated circuits which are best suited for hardware implementations because of the
various advantages it provides like high speed, shorter time to market, reconfiguration and low cost. 
 The proposed architectures are implemented on Spartan-6, Virtex-5 and Virtex-7 devices.
 The percentage improvement with respect to area consumption for proposed TEA, XTEA and XXTEA hardware
architectures are 53.46%, 70.35% and 21.21% respectively. A significant reduction in power consumption for
serial implementation of TEA, XTEA and XXTEA can be observed with percentage improvement of 80%, 81%
and 73.3% respectively.

08/10/2023 Presented by Krishna Pranav, National 54

Institute of Technology, Raipur (Dept of ECE)
 Conclusion and Future Work
In this thesis, optimized implementations of different lightweight ciphers namely TEA, XTEA, XXTEA and LBlock
are proposed. The main objective of the proposed work is to design efficient ways of hardware implementation that
can be best suited for use in IoT applications.

 Chapter 1 provided an introduction of the lightweight cryptography and different design methodologies needed to
design ciphers to form a basis for the work.

 In Chapter 2, literature survey is provided which described the research done in the lightweight cryptography.
The information provided in these chapters helped in designing the proposed lightweight ciphers.

 In Chapter 3, hardware optimization is achieved by designing TEA family lightweight ciphers using serialized
design technique. The serial technique is used to achieve desirable performance for the targeted RFID
application. Improved results are obtained in terms of area and power consumption which are suitable for RFID
applications.

08/10/2023 Presented by Krishna Pranav, National 55

Institute of Technology, Raipur (Dept of ECE)
 Conclusion and Future Work
 In Chapter 4, implementation of XXTEA cipher is proposed for a variable length message. Optimization of area is
observed for the proposed architecture. The LUT count obtained is 213 and the ASIC implementation on 0.18µm
technology suggests area optimized results with GE value of 2922 achieved.

 In Chapter 5, a simple LBlock cipher is implemented which is based on Fesitel structure and uses Substitution and
Permutation logic for the encryption and decryption process. A round based design technique is used to obtain area
optimization. The performance metrics showed improvement in results in terms of area and throughput.

Future Work:

 The significant research findings stated in the thesis provide a basis for further study. The proposed work is focused
on optimizing the selected lightweight ciphers.

 For TEA family ciphers, serial implementation provided optimization in terms of area and power. Further
enhancements can be done in TEA Family ciphers to design more efficient architectures.

 In LBlock cipher, the results obtained for round-based showed low area consumption but more power consumption.
In order to reduce both area and power consumption,
08/10/2023 Presented by serial
Krishnaimplementation
Pranav, National technique can provide efficient results. 56
Institute of Technology, Raipur (Dept of ECE)
 Dissemination
Journals [Under Review]:
1. Apeksha Kamble, Zeesha Mishra and Bibhudendra Acharya, “Optimized Hardware Implementation of TEA
Family Lightweight Cipher,” Institution of Electronics and Telecommunication Engineers (IETE) Journal of
Research.
2.Apeksha Kamble, Zeesha Mishra and Bibhudendra Acharya, “Efficient Hardware Implementations of LBlock and
XXTEA Lightweight Block Ciphers for Resource-Constrained IoT Devices and Sensor Networks,” International
Journal of Ad Hoc and Ubiquitous Computing (IJAHUC).

08/10/2023 Presented by Krishna Pranav, National 57

Institute of Technology, Raipur (Dept of ECE)
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08/10/2023 Presented by Krishna Pranav, National 62
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08/10/2023 Presented by Krishna Pranav, National 63
Institute of Technology, Raipur (Dept of ECE)
 THANK YOU

08/10/2023 Presented by Krishna Pranav, National 64

Institute of Technology, Raipur (Dept of ECE)