Chapter 6 -- Introduction to Sequential Devices

The Sequential Circuit Model

x1 z1
C o m b in atio n al
xn lo g ic zm

(a)

x1 z1
xn C o m b in atio n al zm
lo g ic

y1 yr Yr Y1

M em o ry

(b )

Figure 6.1
 State Tables and State Diagrams

In p u t
P resen t sta te x

N ex t sta te
Y
x /z
In p u t/o u tp u t
y Y/z
P resen t sta te y

N ex t
sta te/o u tp u t
(a ) (b )

Figure 6.2
Sequential Circuit Example
In p u t x
0 1
A D /0 C /1
P resen t B B /1 A /0
sta te C C /1 D /0
D A /0 B /1

(a )

0 /1
1 /1
A C

0 /0
1 /0 1 /0
0 /0

B D
1 /1
0 /1
x /z
(b )

Figure 6.3
Latch and Flip-flop Timing

S et

R eset

(a )

S et

R eset

C lo ck

(b )

Figure 6.4
TTL Memory Elements
 Set Latch

0 1 1
0
0 0 Q 1 Q 0 Q
0 S 0 S 1 S 1
(a ) (b ) (c) (d )

Figure 6.5
 Reset Latch

0
1
0 Q
S 0

(a )

0 1
1 0 0 1
R=0 R=1
1 0
Q Q
(b ) (c)

1 Q
0 1
R=0 Q
0 R
Q
(d ) (e)

Figure 6.6
 Set-Reset Latch (SR latch)
Q Q
N1 N1
S N2 Q S N2 Q
R
(a ) (b )

S
N1 Q
S Q

R Q
N2 Q
R
(c) (d )

Figure 6.7
 NAND SR Latch
S S=0 S=1
S
N1 Q Q

R N2 Q R=0 R=1 Q
R

(a ) (b )

S
Q

Q
R

(c)

S Q S Q

R Q R Q

(d ) (e)

Figure 6.8
Set-Reset Latch Timing Diagram

R
Q

S et R eset S et Illeg a l
in p u ts
U n k n o w n v a lu es
(a )

R
Q

S et R eset S et Illeg a l
in p u ts
U n k n o w n v a lu es
(b )

Figure 6.9
 SR Latch Propagation Delays

S
t PLH
(S to Q )
R t PHL
t PLH (R to Q )
(N 2 )
Q
t PHL
(N 2 ) t PLH
(N 1 )
Q
t PHL
(N 1 )
 SR Latch Characteristics
0d SR d0
10
0 1
E x cita tio n P resen t N ex t
01
in p u ts sta te sta te
S R Q Q* (b )

0 0 0 0 N o ch a n g e
SR S
0 0 1 1
0 1 0 0 R eset Q 00 01 11 10
0 1 1 0
1 0 0 1 S et 0 0 0 Ð 1
1 0 1 1
1 1 0  N o t a llo w ed
1 1 1  Q 1 1 0 Ð 1

(a )
R
(c)

Figure 6.11

Q* = S + RQ
SN74279 Latch with Two Set Inputs

S1
S2 Q
S1
S2 Q

R
Q
R
(a ) (b )

Figure 6.12
 Gated SR Latch

S S S
S Q S Q
C*S Q

C C C

Q
R Q R Q
R R R C* R
(a ) (b )
(c)

S Q

R Q

(d )

Figure 6.13
 Gated SR Latch Characteristics
E n a b le E x cita tio n P resen t N ex t
in p u ts in p u ts sta te sta te
C S R Q Q*
0   0 0 H o ld
0 ´ ´ 1 1
1 0 0 0 0 N o ch a n g e
1 0 0 1 1
1 0 1 0 0 R eset
1 0 1 1 0 0dd, 10d C SR 0dd, 1d0
1 1 0 0 1 S et
1 1 0 1 1 110
1 1 1 0  N o t a llo w ed 0 1
1 1 1 1 
101
(a ) (b )

Figure 6.14

Q* = SC + RQ + C Q
 Delay Latch (D latch)

S S
D D
Q Q
D Q
C C

Q Q

C Q R S R la tc h R S R la tc h

(a ) (b ) (c)

Figure 6.15
 D Latch Characteristics

E n a b le E x cita tio n P resen t N ex t

in p u t in p u t sta te sta te
C D Q Q*
0  0 0 H o ld
0 ´ 1 1 0d, 10 CD 0d, 11
1 0 0 0 S to re 0
1 0 1 0 11
1 1 0 1 S to re 1 0 1
1 1 1 1
10
(a ) (b )

Figure 6.16

Q* = DC + CQ
 D Latch Timing Diagram

E n a b led E n a b led
E n a b led
H o ld H o ld

Figure 6.17
 D Latch Timing Constraints

D m ay not
ch a n g e S etu p tim e H o ld tim e
v io la tio n v io la tio n

D
th
(h o ld ) th
C
tsu tsu
(setu p )
Q

tw
M in im u m en a b le U n k n o w n sta te
p u lse w id th

Figure 6.18
 The SN74LS75 D Latch

D CD D 0
0
C Q C Q
Q Q
1

CQ

(a ) (b )

D D
1
C Q C

0 Q
0

Q Q*
Dt
(c) (d )

Figure 6.19
Propagation Delays and Time Constraints
for the SN74LS75
 Hazard-Free D Latch, the SN74116
D D

1 1

Q 1 1 1 Q 1 1 1

C C
(a ) (b )

P R E (o r S )
D D
C
C1
Q C2 Q
Q
Q

C L R (o r R )
(c) (d )

Figure 6.20

Q* = DC + CQ + DC
 Master-Slave SR Flip-flop
M a ster S la v e
QM
S S Q S Q Q
C C S Q
R R Q R Q Q C
R Q
C
(clo ck ) (a ) (b )

C
S and R m ay
M a ster g a te d h o ld g a te d h o ld g a te d h o ld g a te d h o ld n o t ch a n g e

S la v e h o ld g a te d h o ld g a te d h o ld g a te d h o ld g a te d
R
S
S
t su
R (setu p )
C
th
QM (h o ld )

Q tw tw
C lo w p u lse w id th C h ig h p u lse w id th
(m a ster en a b led ) (sla v e en a b led )
(d )
F lip -flo p o u tp u t ca n ch a n g e
(c)

Figure 6.20
SR Master-Slave Flip-Flop Characteristics

S R Q C Q*
0 0 0 0 N o ch a n g e
0d SR 0d
0 0 1 1
0 1 0 0 R eset 10
0 1 1 0 0 1
1 0 0 1 S et 01
1 0 1 1
(b )
1 1 0  N o t a llo w ed
1 1 1 
(a )

Figure 6.22

Q* = S + RQ
 Master-Slave D Flip-Flop

M a ster S la v e
QM
D D Q D Q Q

D Q
C Q C Q Q

C Q
C
(clo ck ) (a ) (b )

Figure 6.23
Master-Slave D Flip-Flop Characteristics
D Q C Q*
0 0 0 S to re 0
0 D 1
0 1 0
1 0 1 S to re 1 1
1 1 1  

(a ) 0
(b )

E n a b led : M S M S M S M S M

QM

Q = QS

(c)

Figure 6.24

Q* = D
Pulse-Triggered JK Flip-Flop Characteristics
0d JR d0
1d
J K Q C Q* 0 1
d1
0 0 0 0 H o ld
0 0 1 1 (b )
0 1 0 0 R eset JK J
0 1 1 0
Q 00 01 11 10
1 0 0 1 S et
1 0 1 1 0 0 0 1 1
1 1 0 1 T o g g le
1 1 1 0
Q 1 1 0 0 1
(a )

K
(c)

Figure 6.25

Q* = KQ + JQ
 Pulse-Triggered JK Flip Realization

KQ
K
Q*
D Q Q J Q
J C
JQ Q
C Q K Q
C
(b )
(a )

Figure 6.26
The SN7476 Dual Pulse-Triggered JK Flip-Flop
'7 6

(2 )
1PR E S
(4 ) (1 5 )
1J 1J 1Q
(1 )
1CLK C1
(1 6 ) (1 4 )
PR E 1K 1K 1Q
J (3 )
Q Q 1CLR R
C
Q Q (7 )
K 2PR E
CLR (9 ) (1 1 )
2J 2Q
(6 )
(a ) 2CLK
(1 2 ) (1 0 )
2K 2Q
(8 )
2CLR

(b )

Figure 6.27
SN7474 Dual Positive-Edge-Triggered D Flip-Flop

'7 4

PR E (4 )
1PR E S
(3 ) (5 )
1CLK C1 1Q
(2 )
1D 1D
PR E (1 ) (6 )
CLR Q 1CLR R 1Q
Q Q

Q Q (1 0 ) (9 )
2PR E 2Q
Q CLR
CLK (1 1 )
2CLK
(1 2 ) (8 )
(b ) 2D 2Q
(1 3 )
2CLR
D
(a ) (c)

Figure 6.28
 SN7474 Excitation Table

In p u ts O u tp u ts
PRE C LR D C LK Q Q M ode
L H   H L S et
H L   L H C lea r
L L   H H N o t a llo w ed
H H H  H L C lo ck ed o p era tio n
H H L  L H C lo ck ed o p era tio n
H H  L Q0 Q0 H o ld

Figure 6.29
SN7474 Flip-Flop Timing Specifications

T o O u tp u t Q
fro m : D ela y P a ra m eter V a lu e (n s)
C lo ck t PLH 25
D sh o u ld b e sta b le t PHL 40
PR E t PLH 25
th t PHL 40
th CLR t PLH 25
D
t su t PHL 40
t su

C (b )

In p u t M in im u m
Q P in C o n stra in t V a lu e (n s)
t PHL t PLH D t su 20
D th 5
(a ) C lo ck t w lo w 30
C lo ck t w h ig h 37
CLR t w lo w 30
PR E t w lo w 30

(c)

Figure 6.30
SN74175 Positive-Edge-Triggered D Flip-Flop
(4 ) (2 )
1D D Q 1Q
CK (3 )
Q 1Q
CLEAR

(5 ) (7 )
2D D Q 2Q
CK (6 )
Q 2Q
CLEAR

(1 2 ) (1 0 )
3D D Q 3Q
CK (1 1 )
Q 3Q
CLEAR

(1 3 ) (1 5 )
4D D Q 4Q
(9 ) CK (1 4 )
C LO C K Q 4Q
CLEAR
(1 )
C LEAR
(a )

Figure 6.31 (a)

 SN74273 Positive-Edge-Triggered D Flip-Flop

1D 2D 3D 4D 5D 6D 7D 8D
(3 ) (4 ) (7 ) (8 ) (1 3 ) (1 4 ) (1 7 ) (1 8 )
(1 1 )
C LO C K
1D 1D 1D 1D 1D 1D 1D 1D
C1 C1 C1 C1 C1 C1 C1 C1

R R R R R R R R
(1 )
C LEAR
(2 ) (5 ) (6 ) (9 ) (1 2 ) (1 5 ) (1 6 ) (1 9 )
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q

(b )

Figure 6.31 (b)

SN74LS73A Edge-Triggered JK Flip-Flop
Logic Diagram

Q Q

CLR

K J

CLK

Figure 6.32 (a)

SN74LS73A Logic Symbols

'L S 7 3 A
(1 4 )
1J 1J
1 C L (1 ) C (1 2 )
K 1 1Q
1 (3 ) 1
K K
1 C L (2 ) (1 3 )
J R R 1Q
Q
C
Q (7 ) (9 )
K CL 2J 2Q
R 2 C L (5 )
K
2 (1 0 ) (8 )
K 2Q
2 C L (6 )
(b )
R

(c)

Figure 6.32 (b) and (c)

SN74276 and SN74111 Edge-Triggered
JK Flip-Flops
'2 7 6
'1 1 1
P R E (1 1 ) S
C L K (1 ) R 1PRE
(2 )
S
(4 )
1J 1J (7 )
(2 ) (5 ) (5 ) C 1Q
1J 1J C 1Q 1CLK 1
(3 ) 1
1C LK 1 1 (1 )
(4 ) 1K K (6 )
1K (9 ) K (6 ) (3 ) 1Q
2J 2Q 1CLR R
(8 )
2C LK (1 4 )
(7 ) 2PRE (9 )
2K (1 2 ) (1 5 ) (1 2 ) 2Q
3J 3Q 2J
(1 3 )
3C LK (1 1 )
(1 4 ) 2CLK (1 0 )
3K (1 9 ) (1 6 ) (1 5 ) 2Q
4J 4Q 2K
(1 8 )
4C LK (1 3 )
(1 7 ) 2CLR
4K

(d ) (e)

Figure 6.32 (d) and (e)

Negative-Edge-Triggered T Flip-Flop

VC
C

PRE PRE
J
Q Q
T C
Q Q
K
CLR CLR

(a ) (b )

Figure 6.33
Edge-Triggered T Flip-Flop Characteristics

0 T 0
T Q Q*
1
0 1 T o g g le 0 1
1 0 T o g g le
1
(a ) (b )

Figure 6.34

Q* = Q
 Clocked T Flip-Flop

PRE PRE
T J
T Q Q
C
C Q Q
K
C LR C LR

(a ) (b )

Figure 6.35
Excitation Table for Clocked T Flip-Flops

T Q C Q*
0 0  0 H o ld
0 1  1
1 0  1 T o g g le
1 1  0

Figure 6.36

Q* = TQ + TQ
The Clocked T Flip-Flop Timing Diagram

C lo ck 

Dt
Q Q Tc
Tc
T T
C lo ck
Q Q
Q
(a )
Q
(b )

Figure 6.37
Summary of Latch and Flip-Flop Characteristics
 SE555 Precision Timing Module

R eset
VCC
C o n tro l
SE 555
R
C1 R1
T h resh o ld Q
R 1 O u tp u t

S
R
C2

T rig g er

R C o m p a ra to r

Q1 D isch a rg e

G ro u n d

Figure 6.38
Astable Operation of The SE555
VCC

0 .0 1 m F

5 8
RA RL
C ont VCC

4
RESET
7
D IS C H 3
6 O ut
RB THRES S q u a re w a v e
2
T R IG

C GND
1
SE 555

Figure 6.39
Monostable (One shot) Device Realization

VCC

0 .0 1 m F

5 8
RA RL
C ont VCC

4
RESET
7
D IS C H 3
6 O ut O u tp u t
THRES
2
T rig g er T R IG
SE 555
C 3 .3 -m s p u lse if
GND
R A = 3 k O hm and C = 1 m F
1

Figure 6.40
PROM-based Sequential Circuits

In p u t
x
PR O M 1 PR O M 2

N ex t Y
sta te
R eg ister
O u tp u t
z

P resen t sta te y C lo ck
(a )
In p u t
P resen t x
sta te C o n ten ts
PR O M A d d ress PR O M 1 PR O M 2
x y Y z

y Y/z

N ex t sta te/
o u tp u t

(b ) (c)

Figure 6.41
PROM-based Sequential Circuit Example
x
y 2y 1 0 1 0 1 0 1
x
00 1 0 /1 0 0 /1 1 1 1 0
01 1 1 /0 1 1 /1
10 0 1 /1 0 0 /0 2 0 1 1
11 0 0 /0 1 1 /0
3 0 0 0
Y 2 Y 1 /z
y2 4 0 0 1
(a )
y1 5 1 1 1
6 0 0 0
7 1 1 0
Y2 Y1 z
x y2 y1 Y2 Y1 z
0 0 0 1 0 1
0 0 1 1 1 0 D D
0 1 0 0 1 1 C C
0 1 1 0 0 0
1 0 0 0 1 Q Q
0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 1 1 1 0 C lo ck
(b ) (c)

Figure 6.41
 Prime Number Sequencer
256 x 8 PR O M
0
1
2 0 0 0 0 0 0 1 1
3 0 0 0 0 0 1 0 1
4
5 0 0 0 0 0 1 1 1
6
7 0 0 0 0 1 0 1 1
8
9
10
11 0 0 0 0 1 1 0 1 Figure 6.43
12
13 0 0 0 1 0 0 0 1
14

251 0 0 0 0 0 0 1 0
252
253
254
255

1D 2D 3D 4D 5D 6D 7D 8D
C lo ck
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q

SN 74273 C lo ck
(8 D flip -flo p s)