Amirkabir University of

Technology
(Tehran Polytechnic)
Department of Computer Engineering and Information
Technology

Main Memory Management

Hamid R. Zarandi
[email protected]

Hamid R. Zarandi Amirkabir Univ. of Tech. (Tehran Polytechnic) 2015/10/26

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Why memory management?

CPU utilization and increase of performance
 need of scheduler to schedule multiple processes
 they should be resident in RAM (physical memory)

Why need of memory management?

o Having multiple processes
o Protection (processes from one another, processes from OS)

Protection should be done by Hardware than OS (why?)

o Performance penalty and latency

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How to protect process memory space?

Each process has a separate memory space

To protect processes’ spaces

o Determining legal address
 Base register (‫)پایه‬: smallest legal physical memory address
 Limit register (‫)حد‬: size of the range

o Example:
 Base register = 300040
 Limit register = 120900

 Legal address space:

Base <= (any address) < Base+Limit
 Can easily be checked by hardware

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HW address protection (base & limit regs.)

Any illegal address generates a trap exception which is known as fatal error

Who loads Base and Limit registers?

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Address binding

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Address binding
Input Queue
o Processes on disk that are waiting to be brought into memory during execution (Part of
ready queue which is on disk)

How to put a process in a physical address?

o Addresses in source program are symbolic
 Example: count variable

o A compiler binds them to relocatable addresses

 Example: 14 bytes from beginning of this module

o Linker and loader bind them next to absolute addresses

 Example: 74014

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How to bind inst./data to mem. address?

Compile time
o If memory location known a priori, absolute code can be generated;
must recompile code if starting location changes
 Example: COM files in MS-DOS

Load time
o Must generate relocatable code if memory location is not known at
compile time

Execution time
o Binding delayed until run time if the process can be moved during its
execution from one memory segment to another
 Need hardware support for address maps
 Example: Base-Limit registers

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Logical vs. physical address space

Logical address (CPU address)
o CPU logically sees addresses
o Logical address space: set of all logical addresses generated by a program

Physical address (Memory address)

o Address of memory line
o Physical address space: set of all physical addresses generated by a program

May be equal or not

o Equal: compile-time and load-time address bindings
o Not equal: execution-time address binding
 In this case, logical address is said virtual address

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What is MMU (Memory Management Unit)?

 MMU is responsible of mapping virtual

(logical) address to physical address

 Simple version: Base-Limit registers

 Here Base register is called relocation register

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Dynamic linking and loading

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Dynamic loading

Dynamic loading
o A routine is not loaded until it is called

o All routines except main() are kept on disk

o Better space utilization

o Some routines are infrequently needed: error functions

o In the case of call, if it is not loaded, linking loader first loads it to the
memory and update program’s address table to reflect this change

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Dynamic linking
Dynamic linking (Dynamically linked libraries)
o System libraries that are linked to user programs when they are run
o No waste of memory and disk space
o Example: Language subroutines
o Stub: small piece of code used to locate dynamic linked libraries
 Replace itself with the address of the routine & executes the routine
o Also known as Shared Libraries

Static linking
o System libraries are linked to user programs during compile time

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Swapping

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Swapping
Swapping is performed temporarily between
memory and backing store

Backing store – fast disk large enough to

accommodate copies of all memory images for
all users; must provide direct access to these
memory images

 Possible of total process memory spaces exceeds

real physical memory
 Use of Backing store

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Swapping issues
Does the swapped out process need to swap back in to same physical
addresses?
o Depends on address binding method
o Plus consider pending I/O to/from process memory space

Pending IO: cannot swap out as IO would occur to wrong swapped in process!
o Or always transfer IO to kernel space, then to IO device; this is known as double buffering;
adds overheads

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Swapping and modern OSs

Standard swapping is not used in Linux & Windows!

o Modified version is used:
 Swap only when free memory is extremely low (less than threshold)
 Disable swapping when free memory is more than threshold

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Swapping cost
Major part of swap time is transfer time

Total transfer time is proportional to the amount of memory swapped.

Example:
o 100 MB process swapping to hard disk with transfer rate of 50 MB/sec

o Swap out time of 2(sec)+swap in of same size process

o Total context switch swapping component time of 4 sec.

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Memory allocation

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Memory allocation
Different types
1. Contiguous
 Each process is in a single section of memory that is contiguous to sections of others

2. Segmentation
 Each process is divided into different segments; each one is located in different part

3. Paging
 Each process is divided into same–small–size pages; some of them are swapped in/out

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Criteria and problems

 CPU Utilization
o Utilization = Percent of time a CPU is busy =
 Some times is
 Some times is

 Fragmentation
o External
o Internal

 Process locality problem

o Static sparseness
o Dynamic sparseness

 Code/data sharing problem and protection problem

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1) Contiguous allocation
Relocation registers used to protect user processes from each other, and from
changing operating-system code and data
o Base register contains value of smallest physical address
o Limit register contains range of logical addresses
 Each logical address must be less than the limit register

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Multiple-partition memory allocation

o Degree of multiprogramming limited by number of partitions
o Variable-partition sizes for efficiency (sized to a given process’ needs)

o Hole – block of available memory; holes of various size are scattered throughout memory
o When a process arrives, it is allocated memory from a hole large enough to accommodate it

o Operating system maintains information about:

a) allocated partitions b) free partitions (hole)

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Dynamic storage-allocation problem

How to satisfy a request of size n from a list of free holes?

o First-fit: Allocate the first hole that is big enough

o Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless
ordered by size
 Produces the smallest leftover hole

o Worst-fit: Allocate the largest hole; must also search entire list
 Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed and storage
utilization

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Fragmentation problem
External Fragmentation
o Total memory space exists to satisfy a request, but it is not contiguous

Internal Fragmentation
o Not whole of allocated memory is filled by the process memory

 First fit analysis reveals that given N blocks allocated, 0.5 N blocks lost to fragmentation
o 1/3 may be unusable -> 50-percent rule

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Fragmentation solution
Compaction
o Shuffle memory contents to place all free memory together in one large block

o Compaction is possible only if relocation is dynamic, and is done at execution time

o I/O problem
 Latch job in memory while it is involved in I/O
 Do I/O only into OS buffers

o Now consider that backing store has same fragmentation problems

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2) Segmentation
Memory-management scheme that supports user view of memory

A program is a collection of segments

o A segment is a logical unit such as:

 main program
 procedure
 function
 method
 object
 local variables, global variables
 common block
 stack
 symbol table
 arrays

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logical view of segmentation

1

4
1

3 2
4

user space physical memory space

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Segmentation implementation
 Logical address consists of a two tuple:
<segment-number, offset>

Segment table
o Maps two-dimensional physical
addresses; each table entry has:
 base – contains the starting physical
address where the segments reside in
memory
 limit – specifies the length of the
segment

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Example of segmentation

 A reference to byte 53 of segment 2:

4300+53=4353

 A reference to byte 852 of segment 3:

3200+852=4052

 A reference to byte 1222 of segment 0:

Trap to OS!

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3) Paging
 Noncontiguous memory allocations:
o Segmentation
o Paging

 Paging avoids external fragmentation, and need of compaction, whereas segmentation does not.

 Process is allocated physical memory whenever physical memory is available

o Avoid external fragmentation
o Avoid problem of varying sized memory chunks

 Divide physical memory into fixed-sized blocks called frames.

o Size is power of 2, between 512 bytes to 16 Mbytes

 Divide logical memory into blocks of same size called pages.

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Paging
Keep tracks of all free frames

To run a program with N pages, need to find N different free frames
and load program.

Setup a page table to translate logical to physical address

Still have internal fragmentation

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Address translation scheme

CPU address (Logical address) is divided into two parts:
o Page number (p): used as an index into a page table that contains base
register of each page in physical memory

o Page offset (d): combined with base address to define the physical memory
address that is sent to the memory unit.

For given logical address space 2m and page size 2n

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Paging hardware

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Paging model of logical and physical memory

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Paging example

n=2 and m=4, 32-byte memory and 4-byte pages.

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Free frames

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Paging example – Internal fragmentation

Page size = 2048 bytes (2kB)

Process size = 72766 bytes

72766/2048 = 35 pages +1086 bytes

Internal fragmentation: 2048 – 1086 = 962 bytes

Worst case fragmentation: 1 frame – 1 byte

On average fragmentation: ½ frame size

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Small page size vs big page size

On average fragmentation: ½ page size, small page size are good.

Small page size, more overhead is in the page-table, this overhead is reduced
when page size increases.

Disk I/O is more efficient when the amount of data being transferred is larger
(e.g. big pages)

Page typically are between 4 kB and 8 kB in size.

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Page table implementation

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Page table
Page table is kept in memory

Page-table base register (PTBR) points to the page table

Page-table length register (PTLR) indicates size of the page table

In this scheme every data/instruction access requires two memory

accesses:
o One for the page table, another for data/instruction

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Translation look-aside buffer (TLB)

 The two memory access problem can be solved by the use of a special fast-lookup hardware cache
called associative memory or translation look-aside buffer (TLB).

 Associative memory: parallel search

 Address translation (p, d):

o If p is in associative memory, get frame# out
o Otherwise, get frame# from page table in memory

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Paging hardware with TLB

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Effective access time

Hit ratio: percentage of times that a page number is found in the TLB.

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More about TLB

Some TLBs store address-space identifier (ASID) in each TLB entry
o Uniquely identifies each process to provide address-space protection for
that process
o Otherwise, need to flush at every context switch

TLB is typically small (64 to 1024 entries)

On a TLB miss, value is loaded into the TLB for faster access next
time.
o Replacement policies must be considered.

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Memory protection

Memory protection is implemented by protection bit with each frame to

indicate if read-only or read-write access is allowed.

Valid-invalid bit attached to each entry in page table:

o Valid indicates that the page is in the process logical address space (legal page)
o Invalid indicates that the page is not in the process logical address space (illegal page)
o Or use page-table length register (PTLR)

Any violation result in trap to the kernel

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Valid/invalid bit in a page table

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Shared pages

Shared code
o One copy of read-only (reentrant) code shared among processes (e.g., text editors)
o Similar to multiple threads sharing the same process space.

Private code and data

o Each process keeps a separate copy of the code and data
o The page for the private code and data can appear anywhere in the logical address space

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Shared pages - Example

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Problem of big page tables

Memory structure for paging can get huge using straight-forward
methods.

Consider a 32-bit logical address space on a modern computers:

o Page size of 4 kB = 212
o Page table would have 1 million entries (232 /212)
o If each entry is 4 B: 4 MB of physical address space memory for page table
alone.
o The amount of memory used, cost a lot
o Don’t want to allocate that contiguously in the memory

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Solutions to maintain huge page tables

A) Hierarchical paging

B) Hashed page tables

C) Inverted page tables

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A) Hierarchical paging
Use of two-level page table!
We then page the page table!

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Two-level paging - example

 A logical address, on 32-bit machine with 1 kB page size, is divided:
o A page offset consisting 10 bits
o A page number consisting of 22 bits

 Since the page table is paged, the page number is divided into:
o A 12-bit page number
o A 10 bit page offset

 Thus a logical address is:

where p1 is an index into outer page table, and p2 is the displacement within the page of inner page
table
 Known as forward-mapped page table
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Address-translation scheme

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64-bit logical address space

Even two-level paging scheme is not sufficient

If page size of 4 kB (212)

o Page table entries = 252
o Assuming each page table entry size = 4 B
o If two-level scheme, inner page table could be 210, 4 kB entries
o Outer page table has 242 entries or 244 B
o Address would look like:

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Three-level paging scheme

One solution is to add a 2nd outer page table

But in the following example, the 2nd outer page table is still 234 bytes in size!

And possible 4 memory access to get to one physical memory location:

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B) Hashed page tables

Common in address space > 32 bits

The logical page number is hashed into a page table

This page table contains a chain of elements hashing to the same location

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Hash page table scheme

Each element contains

o Logical page number
o Physical frame number
o Pointer to the next node

Search is done serially

in the linked list

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C) Inverted page table

Rather than keeping all possible logical page numbers, track all physical pages
(frame) numbers

One entry for each physical page of memory

Entry consists of
o Virtual address of the page stored in that frame
o + Process info

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Inverted page table scheme

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Problem and solutions

Good:
o Decrease memory needed
Bad:
o Increase time needed to search the table

Use hash table to limit the search to one, or at most a few, page-table entries.

How to implement shared memory?

o One mapping of a virtual address to the shared physical address

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Questions?

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