02 Word Size and Data Type
02 Word Size and Data Type
each operation
Example: 32-bit Machines are built to
do 32-bit math most optimally
Units of Operation [S3]
Core CPU Registers
N-bit
• Cortex-M Processors has General Registers
N-bit ALU
and Special Purpose CPU Core
registers
• R0-R12 General Purpose N-bit Data Bus (internal)
• R13-R15 Reserved Role
• Program Status Registers
CPU operand size = data size of registers
• Exception Mask Registers
N-bits wide
• Control Register
Instruction Sizes [S4]
• Instruction size can vary
• ARM Instruction Set ARMv6-M 16-Bit and 32-Bit
• Thumb-2 Instruction Set 16-Bit
000104c8 <main>:
104c8: b5b0 push {r4, r5, r7, lr}
16-Bit
Example Output with 104ca: b096 sub sp, #88
Instructions
Machine Code and 104cc: af00 add r7, sp, #0
Assembly Code 32-Bit 104ce: f241 0330 movw r3, #4144
Instructions 104d2: f2c0 0302 movt r3, #2
can be
signed long int
At least 32-bits [-215, +215 – 1]
int32_t
#endif /* __STDINT_H__ */