DX Processor-80386
• CISC architecture
• full 32bit version Microprocessor
– 32bit Data Bus(D0-D31)
– 32bit Address Bus(A2-A31,BE0-BE3)
– 32bit register size(EAX,ABX,ESI…..)
• Operating frequency (10MHz-40MHz)
– We used 33MHz processor operating at
12.5MHz
Buffering System
• Needed to increase fan out
• Used to protect Processor from
unexpected signals
• 74f244 try-state buffers for address bus
and control signals, and 74f245 by-
directional try-state buffers for data
busee
Control Signals
• CLK2: use 25MHz to Operate processor at
12.5 MHz
• Reset: cause to begin executing software
at physical address 0xFFFF0
• Ready: used to generate wait states
used 4 wait states for each Memory or IO
assess (read /write)
Control Signals
• BS16: used to select 16 bit data bus mode
– We used 16 bit data bus.
• M/IO’, W/R’,D/C’, and ADS are used to control
reading and writing on Memory and IO
devices, and to generate Interrupt
Acknowledgement.
• Other control lines are used to connect
coprocessor (we didn’t use it), but have to be
taken in mind.
Memory Interface
• real mode operating
• 1Mbyte memory size 0x00000-0xFFFFF
divided to 16 segments each of 64Kbyte
• used two chips 27c512-150ps
0xe0000-0xFFFFF
• and two chips 61 256 D-RAM (one
segment )as shadowing for the rest of
memory
IO Interface
• 80386-Dx provides 16 bits for interfacing
IO devices which means 64k different IO
addresses
• Using decoding system to decode IO
devices, a few IO addresses are needed,
so Decoder 74F138 is an suitable.
IO devices used
• 82c55A parallel peripheral interface
– IO address 0xFF00 -Port A
– IO address 0xFF04 -Port B
– IO address 0xFF08 -Port C
– IO address 0xFF0C –Control Port
IO devices used
• 8259 Interrupt Controller
– IO Address 0xFF10 -firs Port
– IO Address 0xFF14 -second Port
IO devices used
• PIC16f877 (running at 20 MHz)
• Using PSP to connect PIC to the
Microprocessor.
• We used one output bit from the PIC to tell
the processor if PIC is ready or not.
• By reading IO port 0xFF40 and testing
least significant bit CPU will Know the
state of the PIC.
PIC Commands Format
• If the PIC is ready CPU can send
Commands to the PIC. Each command
consist of :-
– command type’4bits’
– and data length’4bits’
• followed by payload.
PIC Peripherals
• PS-2 Keyboard
• Serial Port
• Graphical LCD (8 rows X 30 columns )
In addition to PSP to achieve
communication between PIC and MP
Additional IO for future use
• Real time Clock bq3287
• 16 bit ISA bus.
Hardware Circuits
ram address decode circut
U13A
A17 1
A18 2 12 CS 27c512
A19 13
1
74F10 U14A
74F04
2
CS 62256
U20A
1 BE0'
3
2 BE2'
U21D U21C
12 9
A0 BLE11 8 74F00
13 10
74F00 74F00 U21B
4 U16A BE0'
6
5 2 1 BE1'
74F00
74F04
U21C U21D
9 12 BE0'
A1 8 11
10 13 BE1'
74F00 74F00
U21B U21A
4 1 BE3'
BHE 6 3
5 2 BE1'
74F00 74F00
IO decoder Vcc
CS_8255 0xFF0X 15 1 A4
CS_8259 0xFF1X 14 Y0 A 2 A5 R2 10k
0xFF2X 13 Y1 B 3 A6
CS_PIC16f877 0xFF3X 12 Y2 C
CS_PIC ready 0xFF4X 11 Y3 6
10 Y4 G1 4 A7
9 Y5 G2A 5 A7
7 Y6 G2B
Y7
74F138
10k
IO write U22A
5 2
6 Q D Vcc
Q 3 ADS
CLK
1 R1 10k
CLR 4 READY' IO decoder
PRE int_ack 15 1 r/w'
74F74 don_occare 14 Y0 A 2 c/d'
IO_read 13 Y1 B 3 m/io'
Mem write U23B IO_write 12 Y2 C
9 12 M_code read 11 Y3 6
8 Q D HLT 10 Y4 G1 4
Q 11 ADS M_data read 9 Y5 G2A 5
CLK M_data write 7 Y6 G2B
13 Y7
CLR 10 READY' 74F138
PRE 0
74F74
U24A
Mem read 2 M_code read
3
1 M_data read MEMOR /IO (READ/WRITE)
Interrupt Control
74F08 segnals
U26A
Mem write 1 BH write
3
BHE 2
74F32
U27B
Mem write 4 BL write
6
BLE 5
74F32
U9
J4 4 34 d0
3 PA0 D0 33 d1
1 2 2 PA1 D1 32 d2
3 4 1 PA2 D2 31 d3
5 6 40 PA3 D3 30 d4
7 8 39 PA4 D4 29 d5
9 10 38 PA5 D5 28 d6
11 12 37 PA6 D6 27 d7
13 14 PA7 D7
15 16 18 9 a2
17 18 Vcc 19 PB0 A0 8 a3
19 20 20 PB1 A1
21 22 21 PB2 35 386 reset
23 24 22 PB3 RESET 5 IO read
25 26 23 PB4 RD 36 IO write
27 28 24 PB5 WR 6 82c55 cs 0xFF0X
29 30 25 PB6 CS
31 32 PB7
33 34 14
35 36 15 PC0
37 38 16 PC1
39 40 17 PC2
13 PC3
12 PC4
11 PC5
40 bin Connector 10 PC6
PC7
82C55
0
Vcc
R3
RESISTOR
R2
U12
1 2 18 11 d0
3 19 IR0 D0 10 d1
4 20 IR1 D1 9 d2
5 21 IR2 D2 8 d3
0 6 22 IR3 D3 7 d4
7 23 IR4 D4 6 d5
RESISTOR SIP 9 8 24 IR5 D5 5 d6
9 25 IR6 D6 4 d7
IR7 D7
a2 27 12
A0 CAS0 13
INTA 26 CAS1 15
IO read 3 INTA CAS2
IO write 2 RD 16
8259 cs 0xFF1X 1 WR SP/EN
CS 17 INT
INT
8259A
