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Module 3

This document discusses different types of interconnect systems used in multiprocessor systems, including hierarchical bus systems, crossbar switches, and multistage networks. It provides details on how each system is structured and operates, as well as their advantages and limitations. Hierarchical bus systems use a tree structure with local, backplane, and I/O buses. Crossbar switches allow direct connections between processors and memory but only scale to small systems. Multistage networks can build larger multiprocessors but connections may require multiple hops.

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18 views25 pages

Module 3

This document discusses different types of interconnect systems used in multiprocessor systems, including hierarchical bus systems, crossbar switches, and multistage networks. It provides details on how each system is structured and operates, as well as their advantages and limitations. Hierarchical bus systems use a tree structure with local, backplane, and I/O buses. Crossbar switches allow direct connections between processors and memory but only scale to small systems. Multistage networks can build larger multiprocessors but connections may require multiple hops.

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sheenanees
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MODULE 3

7.1 MULTIPROCESSORS AND MULTI-COMPUTERS

• M ULTIPROCESSOR SYSTEM INTERCONNECTS

• system interconnects for fast communication among multiple processors and


shared memory, I/O, and peripheral devices.
• Hierarchical buses. crossbar switches. and multistage networks are often
used for this purpose.
INTER CONNECTION SYSTEM IN A GENERALIZED
MULTIPROCESSOR SYSTEM
• Operational characteristics of interconnect network.
• timing protocol, switching method, and control strategy.
• Dynamic networks are used in multiprocessors in which the interconnections
are under program control.
• timing control – synchronous or asynchronous.
• A network can transfer data using either circuit switching or packet switching.
• Network control strategy is classified as central and distributed.
• With central control, a global controller receives requests from all devices
attached to the network and grants the network access to one or more
requesters.
• In a distributed system, requests are handled by local devices independently.
7.1.1 HIERARCHICAL BUS SYSTEMS
• A bus system consists of a hierarchy of buses connecting various system and
subsystem components in a computer.

• Each bus is formed with a number of signal, control, and power lines.

• Different buses are used to perform different interconnection functions.

• The hierarchy of bus systems are packaged at different levels as shown in the
next slide including local buses on boards, backplane buses, and I/O buses.
• Local Bus: Buses implemented Within processor chips or on printed-circuit
boards are called local buses.
• provides a common communication path among major components (chips)
mounted on the board.
• A memory board uses a memory bus to connect the memory with the interface
logic.
• An I/O or network interface chip or board uses a data bus.
• Backplane Bus: is a printed circuit on which many connectors are used to plug in
functional boards.
• A system bus consisting of shared signal paths and utility lines, is built on the
backplane.
• This system bus provides a communication path along all plug-in boards.
• backplaue bus standards – VME bus {IEEE Standard 10l4-1987), Multibus II
[IEEE Standard 1296-1987), and Futurebus+ [[EEE Standard 896.1-I991)
• I/O Bus: Input /output devices are connected to a computer system through an
I/O bus such as the SCSI (Small Computer Systems Interface) bus. This bus is
made of coaxial cables with taps connecting disks, printer, and other devices to a
processor through an I/O controller .

• Hierarchical Buses and Cache: This is a multilevel tree structure in which the
leaf nodes are processors and their private caches . These are divided into several
clusters, each of which is connected through a cluster bus.
• Proposed by Wilson

• An inter-cluster bus is used to provide communications among the clusters.


Second level caches (denoted as C2,) are used between each cluster bus and the
inter-cluster bus.
• Each second-level cache must have a capacity that is at least an order of
magnitude larger than the sum of the capacities of all first-level caches connected
beneath it.
EXAMPLE :ENCORE ULTRAMAX
MULTIPROCESSOR ARCHITECTURE
• Its a two-level hierarchical-bus architecture
• Encore Multimax multiprocessor was the Nanohus, consisting of 20 slots, a 32-
bit address, a 64-bit data path, and a 14-bit vector bus, and operating at a clock
rate of l2.5 MHz with a total memory bandwidth of 100 Mbytes/s.

• Hierarchical bus systems can be used to build medium- sized multi proccssors
with less than 100 processors.
• The approach is limited by bandwidth scalability and the packaging technology
employed.
• The idea of using bridges between multiprocessor clusters is to allow
transactions initiated on a local bus to be completed on a remote bus.

• The main functions of a bridge include communication protocol conversion,


interrupt handling in split transactions, and serving as cache and memory
agents.
CROSSBAR SWITCH AND MULTI PORT MEMORY

• Switched networks provide dynamic interconnections between the inputs and


outputs.
• Crossbar networks are mostly used in small or medium-size systems.
• Major classes of switched networks are based on the number of stages and
blocking or non blocking.
• Network Stage: Depending on the inter-stage connections used, a single stage
network is also called a recirculating because data items may have to recirculate
through the single stage many times before reaching their destination.
• A single stage network is cheaper to build, but multiple passes may be needed to
establish certain connections.
• The crossbar switch and multiport memory organization are both single-stage
networks.
• A multistage network consists of more than one stage of switch boxes. Such a
network should be able to connect from any input to any output.
• The Omega network, Flip network, and Baseline networks are all multistage
networks.
• Blocking versus Non blocking Networks : A multistage network is called
blocking if the simultaneous connections of some multiple input-output pairs
may result in conflicts in the use of switches or communication links.
• Examples of blocking networks include the Omega , Baseline, , Banyan and
Delta networks.
• multistage networks are blocking in nature.
• In a blocking network, multiple passes through the network may be needed to
achieve certain input-output connections.
• A multistage network is called non blocking if it can perform all possible
connections between inputs and outputs by rearranging its connections.
• In such a network, a connection path can always be established between any
input-output pair.
• Eg: The Benes networks
CROSS BAR NETWORK
• Every input port is connected to a free output port through a cross point switch
without blocking.

• Once the data is read from the memory, its value is returned to the requesting
processor along the same cross-point switch.

• such a crossbar network requires the use of n X m crosspoints switches.

• A square crossbar {n = m) can implement any of the n! permutations without


blocking.

• Each crosspoint in a crossbar network is a unary switch which can be set open or
closed, providing a point- to-point connection path between the source and
destination.
• All processors can send memory requests independently and asynchronously.
• This poses the problem of multiple requests destined for the same memory
module at the same time.
• In such cases, only one of the requests is serviced at a time.

• Crosspoint Switch Design


• Out of the n cross-point switches in each column of an n >< m crossbar
mesh, only one can be connected at a time.
• To resolve the contention for each memory module, each cross-point switch
must be designed with extra hardware.
• each cross-point switch requires the use of a large number of connecting
lines accommodating address, data path, and control signals.
• This means that each cross-point has a complexity matching that of a single
bus of the same width.
• For an n>< n crossbar network, this implies that n² sets of cross-point
switches and a large number of lines are needed.
• So far only relatively small crossbar networks with n <=16 have been built into
commercial machines.

• On each row of the crossbar mesh, multiple cross-point switches can be


connected simultaneously.

• Simultaneous data transfers can take place in a crossbar between n pairs of


processors and memories.
• Multiplexer modules are used to select one of n read or write requests for
service.

• Each processor sends in an independent request, and the arbitration logic makes
the selection based on certain fairness or priority rules.
• For example, a 4-bit control signal will be generated form n = I6 processors.
Note that n sets of data, address, and read-write lines are connected to the input
of the multiplexer tree.
• Based on the control signal received, only one out of n sets of information lines
is selected as the output of the multiplexer tree.
• The memory address is entered for both read and write access.
• the data fetched from memory are returned to the selected processor in the
reverse direction using the data path established .
• In the case of write, the data on the data path are stored in memory.
• Acknowledge signals are used to indicate the arbitration result to all requesting
processors.
• These signals initiate data transfer and are used to avoid conflicts.
LIMITATION
• A crossbar network is cost-effective only for small multiprocessors with a few
processors accessing a few memory modules.
• A single-stage crossbar network is not expandable once it is built.
• Redundancy or parity-check lines can be built into each cross-point switch to
enhance the fault tolerance and reliability of the crossbar network.
MULTIPORT MEMORY
 to move all cross-point arbitration and switching functions associated with each
memory module into the memory controller
 Thus the memory module becomes more expensive .
 Only one of the processor requests can be honored at a time.
 The multiport memory must resolve conflicts among processors.

 drawback is the need for a large number of interconnection cables and


connectors when the configuration becomes large.
MULTISTAGE AND COMBINING NETWORKS
• Multistage networks are used to build larger multiprocessor systems.
•
 A number of a>< b switches are used in each stage.
 The switches can be dynamically set to establish the desired connections
between the inputs and outputs.
 Different classes of MINs differ in the switch modules used and in the
kind of inter-stage connection [ISC] patterns used.
 The ISC pattern often includes –
 Perfect shuffle ,multiway shuffle ,butterfly ,cross bar, cube
connections.
 These are data routing functions for inter PE data exchange.

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