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Module 4 Mbist

The document discusses defects, faults, errors and failures in electronic systems. It then summarizes different test approaches including ad-hoc testing, structured methods like scan testing, partial scan, built-in self-test (BIST) and boundary scan. The rest of the document discusses design-for-test (DFT) techniques like controllability and observability, types of scan testing, BIST architectures, fault models, DFT flow and various March test algorithms.

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32 views

Module 4 Mbist

The document discusses defects, faults, errors and failures in electronic systems. It then summarizes different test approaches including ad-hoc testing, structured methods like scan testing, partial scan, built-in self-test (BIST) and boundary scan. The rest of the document discusses design-for-test (DFT) techniques like controllability and observability, types of scan testing, BIST architectures, fault models, DFT flow and various March test algorithms.

Uploaded by

yamini
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 43

DFT-MBIST

D.P.Balsubramanian
SEMI-DFT
DEFECT,FAULT,FAILURE
• DEFECT
A defect in an electronic system is the unintended difference between the
implemented hardware and its intended design. Defects can be Process
Defects, Material Defects, Age Defects, and Package Defects.
• FAULT
A representation of a “defect” at the abstracted function level is called a
fault. A fault (or failure) can be either a hardware defect or a
software/programming mistake (bug).
• ERROR
A wrong output signal produced by a defective hardware at module level
is called an error. An error is an “effect” whose cause is some “defect.”
• FAILURE
A wrong output signal produced by a defective hardware at module level
is called an error. An error is an “effect” whose cause is some “defect.”
DEFECTS
Test Approaches

• Ad-hoc testing
• Structured Method
– Scan
– Partial Scan
– Built-in self-test
– Boundary scan
DFT
TESTABILITY:
A fault is testable if there exists a well-specified procedure (e.g., test pattern
generation, evaluation, and application) to expose it, and the procedure is
implementable with a reasonable cost using current technologies

Goals of Design-for-Test (DFT)


Make testing of manufactured part swift
DFT Mantra
Provide controllability and observability
Components of DFT strategy
• Provide circuitry to enable test
• Provide test patterns that guarantee reasonable coverage

Exhaustive test is impossible or unpractical


DFT
• Controllability
– It is a measure of the difficulty of setting internal
circuit nodes to 0 or 1 by assigning values to
primary inputs (PIs)
• Observability
– It is a measure of the difficulty of propagating a
node’s value to a primary output (PO)
FAULT MODEL
• Stuck-at fault model
• Stuck-Open and Stuck-Short faults
• Bridging faults
• Opens
• Delay faults
• Parametric faults
• Power disturbance faults
DFT FLOW
Boundary scan

Scan insertion

EDT

ATPG

MBIST & OCC


Types of SCAN
• MUXed Scan ƒ
• Scan path ƒ
• Scan-Hold Flip-Flop ƒ
• Serial scan ƒ
• Level-Sensitive Scan Design (LSSD) ƒ
• Random access scan
SCAN based test

ScanIn ScanOut

Out
In Combinational Combinational
egister

egister
Logic Logic
R

R
A B
Boundary SCAN
BIST Architecture
Memory model
Fault models
• Address Decoder faults
• Stuck at Faults
• Transition Faults
• Neighbourhood Pattern Sensitive Fault (NPSF)
– Active NPSF (ANPSF)
– Passive NPSF (PNPSF)
– Static NPSF (SNPSF)
• Coupling faults (CF s )
– Different t ypes of CFs
• Inversion CF(Cfin)
• Idempotent CF(Cfid)
• State CF(CFst)
• Dynamic CF(CFd)
Memory Fault models
Memory Fault models
Memory fault Model
Neighbourhood pattern sensitive fault
Address Decoder Fault
MBIST controller
MBIST Architectures
• (1) a hardwired-based
• (2) microcode-based
• (3) processor-based.
Hardwired Based
Micro code Architecture
Processor Based Architecture
Algorithms
• Two types
– Classical tests
– March-based tests
Classical Test Algorithm
• Classical test algorithms
(1) simple, fast but have poor fault coverage,
such as Zero-one, Checkerboard.
(2) have good fault coverage but complex and
slow, such as Walking, GALPAT, Sliding
Diagonal, Butterfly, MOVI.
Walking 1/0
• Writing a 1 at the first memory location and
writing a 0 in all other memory location
• Increment the memory address and shift the 1
by one position and remaining all bits to be 0
• Continue the above process until it reaches
the last memory location.
March-based Test Algorithms
• A March-based test algorithm is a finite
sequence of March elements. A March
element is specified by an address order and a
number of reads and writes.
• Since March-based tests are all simple and
possess good fault coverage, they are the
dominant test algorithms implemented in most
modern memory BIST.
• March-based tests are MATS, MATS+, Marching
1/0, March C-, March Y, March A, March B.
March C-(evolved March C)
• March C- is a classical algorithm which is the
foundation of other algorithms
• {(w0);(r0,w1);(r1,w0);(r0,w1); (r1,w0);  (r0)}
• Complexity—5N=>O(N)
•  ascending order
•  descending order
• r0:read 0
• w1:write 1
• March Element (w0): M0

30
{(w0);(r0,w1);(r1,w0);(r0,w1); (r1,w0); (r0)}
M0 M1 M2 M3 M4 M5

• Address Fault, Transition Fault: M2 and M3


M1 M2
0 1 1 0
0 1 1 0
0 1 1 0

• Stuck-At Fault: overwrite 0’s and 1’s


M2
1 0
1 0
1 0

31
{(w0);(r0,w1);(r1,w0);(r0,w1); (r1,w0); (r0)}
M0 M1 M2 M3 M4 M5

• Coupling Fault (CF)


– j< i, Cj affected by Ci
– M1: Ci 1->0 falling behavior affect Cj
– M2: Ci 0->1 raising behavior affect Cj
M1 M2
0(j 1 0
) 0 1 1 0
1 0 1 1 0
2(i
)
– j> i, detected by M3 and M4
32
Other March algorithm
SAF AF TF CF
MATS ALL Some
MATS++ ALL ALL
March X ALL ALL ALL Some
March C- ALL ALL ALL ALL
March A ALL ALL ALL Some
March B ALL ALL ALL Some
March Y ALL ALL ALL Some

33
Test for Stuck-at, Transition and coupling
fault
Tools used commercially
• Mentor graphics –tessent shell
• Cadence
• synopsis
Thank you
wish you all Best luck!

See you all in ALTRAN

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