Design and Implementation of Full Adder
using Different XOR Gates
TEAM MEMBERS PROJECT GUIDE
1.P.SANDHYA 17P31A0441 U. SAI SRI RAMYA
M. TECH
2.D.V.S.PHANINDRA 17P31A0458 ASST PROFESSOR
3.P.MITHUN 17P31A0443 DEPARTMENT OF ECE
4.M.S.G.VARMA 17P31A0433 ACET
Contents
ABSTRACT
INTRODUCTION
EXISTING TECHNIQUES
CONCLUSION
Abstract
A Full Adder is a logical circuit that serves a great part in the design of
application particular Integrated circuits. It is the basic component found in
VLSI and DSP applications.
Power consumption is one of the most significant parameters of full adder.
Therefore, reducing power consumption in full adder is very important. In this
paper, we design XOR gate using Transmission gate logic (TGL), Pass transistor
logic (PTL) and Static Complementary metal oxide semiconductor logic
(CMOS).
These circuits are designed, implemented and simulated using Mentor Graphics
180nm technology. Here we compare different XOR gate designs based full
adders in terms of power consumption and delay.
INTRODUCTION
There are different type of arithmetic operations like Addition, Multiplication, Subtraction,
Division e.t.c,. In VLSI systems most commonly used operation is Addition.
The full adders can be implemented using different technologies and the important goal of
these technologies is to reduce power consumption and also to increase speed.
The adder performance can be improved by two methods they are System level viewpoint
method and Circuit style viewpoint method.
System level viewpoint, in this longest signal path is determined in ripple adders and also
decrease the trail to scale back the full signal path delay. Where, the carry out bit of highly
significant bit is calculated there will be a longest path.
INTRODUCTION
In Circuit style viewpoint method, high performance full adder is designed by using
semiconductor level design skills. To prevent decrease in signal magnitude, we require an
optimized design, which also consume less power, provide small delays.
A range of nano meter devices faces the problem of short channel effects and other hot
carrier effects.
To maintain correct speed, the threshold voltage is scaled down, which leads to increase in
standby currents, also effect the static power is one of the main contributor to total power
EXISTING TECHNIQUES
Mostly, By using XOR, AND, OR gates full adders are designed.
While designing full adder, the major consumer of power is XOR
gate.
The power consumption will be decreased in full adder, by
designing the XNOR/XOR gates in an optimum way.
EXISTING TECHNIQUES
XOR GATE USING CMOS LOGIC
CMOS devices will have two important
characteristics
I. High Noisy Immunity and
II. Low Static Power
EXISTING TECHNIQUES
XOR GATE USING TRANSMISSION GATE
LOGIC
It is a switch based upon CMOS, in which
NMOS passes a good output 0 but weak 1, and
PMOS passes good output of 1 but weak 0.
These two transistors, PMOS and NMOS
work parallelly.
EXISTING TECHNIQUES
XOR USING PASS TRANSISTOR LOGIC
The number of transistors count to make different
type of logic is reduced, by deleting the redundant
transistors. Instead of switches we use transistors to
pass logic levels between nodes of a circuit, because
they are directly connected to supply voltages
CONCLUSION
Compared to all the techniques, the Pass Transistor logic based full adder consists
of a very less number of transistors.
So less number of transistors results in less switching activity and area
So by using Pass Transistor logic based full adder, we try to reduce power
consumption and delay when compare with other logic styles based full adder.
Thank You
