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Lec11 Slides Verification Overview

This document discusses design verification through test benches. It provides an overview of how to write test benches that automatically test a design through simulation, check the results for correctness, and flag any errors to the user. It then gives an example of a test bench that could be used to verify a 4-bit adder circuit by generating all possible input combinations and comparing the expected output to the actual output from the adder.

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38 views14 pages

Lec11 Slides Verification Overview

This document discusses design verification through test benches. It provides an overview of how to write test benches that automatically test a design through simulation, check the results for correctness, and flag any errors to the user. It then gives an example of a test bench that could be used to verify a 4-bit adder circuit by generating all possible input combinations and comparing the expected output to the actual output from the adder.

Uploaded by

Abdalrhman juber
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Advanced Digital Design

ENCS3310

Design Verification Overview


Introduction

 How to write test benches:


 Test out design in simulation
 Automatically decide if the design works
 Flag errors to the user
A Proper Test Bench

 The test benches we have used so far have not been


complete testbenches for verification purposes
 A full testbench
 runs a simulation
 automatically checks the answers for correctness
 notifies the user of any error
Example: adder circuit

 Example of earlier lectures: 4-bit adder


 We’ll write a test bench
cin

x
y
0 + sum Result of 4 bit addition
0
0 cry needs 5 bits to represent
x 1
1 + sum
y 1
1 cry
2
x
2 + sum
y 2
2 cry
3
x
3 +
y sum
3 3

cout
Test Bench Example
Expected result
0
4
TestIn1 cin
Generate x 4
tests 4 sum AdderOut
y Analyze
TestIn2 cout

AdderCarry Print warning if


differences found

 Full test bench for adder example


 TestIn1 and TestIn2 will cycle through all possible values
 Correct output will be calculated
 Discrepancies will be reported
Test Bench Entity
Expected result
0
4
TestIn1 cin
Generate x 4
tests 4 sum AdderOut
y Analyze
TestIn2 cout

AdderCarry Print warning if


differences found

module adder_test;
endmodule
Test Bench Architecture
Expected result
0
4
TestIn1 cin
Generate x 4
tests 4 sum AdderOut
y Analyze
TestIn2 cout

AdderCarry Print warning if


differences found
module adder_test;
//Declarations of test inputs and outputs (reg and wire)

//Place one instance of test generator


test_generator TG(connections)
//Place one instance of the Unit Under Test
adder4 DUT(connections)
//Place one instance of result analyzer
result_analyzer RA(connections)
endmodule
Test Bench Architecture
Expected result
0
4
TestIn1 cin
Generate x 4
tests 4 sum AdderOut
y Analyze
TestIn2 cout

AdderCarry Print warning if


differences found
module adder_test;
//Declarations of test inputs and outputs

//Place one instance of test generator


test_generator TG(connections)
//Place one instance of the Unit Under Test
adder4 DUT(connections)
//Place one instance of result analyzer
result_analyzer RA(connections)
endmodule
Test Bench Architecture
Expected result
0
4
TestIn1 cin
Generate x 4
tests 4 sum AdderOut
y Analyze
TestIn2 cout

AdderCarry Print warning if


differences found
module adder_test;
//Declarations of test inputs and outputs

//Place one instance of test generator


test_generator TG(connections)
//Place one instance of the Unit Under Test
adder4 DUT(connections)
//Place one instance of result analyzer
result_analyzer RA(connections)
endmodule
Test Bench Architecture
Expected result
0
4
TestIn1 cin
Generate x 4
tests 4 sum AdderOut
y Analyze
TestIn2 cout

AdderCarry Print warning if


differences found
module adder_test;
//Declarations of test inputs and outputs

//Place one instance of test generator


test_generator TG(connections)
//Place one instance of the Unit Under Test
adder4 DUT(connections)
//Place one instance of result analyzer
result_analyzer RA(connections)
endmodule
TG: Generating the Test Inputs
 Loop all possible values (use for loop) or repeat…etc.
 Produce the behavioural output using direct operations
RA: Checking for Errors
ASSERT condition REPORT message

Assertion is not supported in Verilog, but we can build a


task and make assertion inside

SEVERITY severity;
Doing the Automatic Checking

ASSERT ExpectedResult(3 DOWNTO 0) = ActualAdd


and ExpectedResult(4) = ActualCarry
PRINT "Adder output is incorrect"
Running our testbench

 Simulation goes through all possible inputs


 Reports any discrepancies between required output
and actual output

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