Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

Designing Sequential
Logic Circuits
November 2002
© Digital Integrated Circuits2nd
Sequential Circuits
 Sequential Logic
Inputs Outputs
COMBINATIONAL
LOGIC

Current State
Next state
Registers
Q D

CLK

2 storage mechanisms
• positive feedback
• charge-based

© Digital Integrated Circuits2nd

Sequential Circuits
 Naming Conventions
 In our text:
 a latch is level sensitive
 a register is edge-triggered
 There are many different naming
conventions
 For instance, many books call edge-
triggered elements flip-flops
 This leads to confusion however

© Digital Integrated Circuits2nd

Sequential Circuits
 Latch versus Register
 Latch  Register
stores data when stores data when
clock is low clock rises

D Q D Q

Clk Clk

Clk Clk

D D

Q Q

© Digital Integrated Circuits2nd

Sequential Circuits
 Latches
Positive Latch Negative Latch

In D Q Out In D Q Out
G G

CLK CLK

clk clk

In In

Out Out

Out Out Out Out

stable follows In stable follows In

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Sequential Circuits
 Latch-Based Design
• N latch is transparent • P latch is transparent
when  = 0 when  = 1


N P
Logic
Latch Latch

Logic

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Sequential Circuits
 Timing Definitions

CLK
t Register
tsu t hold D Q

D DATA CLK
STABLE t
tc 2 q

Q DATA
STABLE t

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Sequential Circuits
 Characterizing Timing

tD 2 Q

D Q D Q

Clk Clk

tC 2 Q tC 2 Q

Register Latch

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Sequential Circuits
 Maximum Clock Frequency


FF’s

LOGIC Also:
tcdreg + tcdlogic > thold
tp,comb
tcd: contamination delay =
minimum delay
tclk-Q + tp,comb + tsetup = T

© Digital Integrated Circuits2nd

Sequential Circuits
 Positive Feedback: Bi-Stability

© Digital Integrated Circuits2nd

Sequential Circuits
 Meta-Stability
Vi1 is excited by small deviation d
A A
Vi2 5 Vo1

Vi2 5 Vo1
C C

B B
Vi1 5 Vo2 Vi1 5 Vo2
d d
Gain should be larger than 1 in the transition region
Only A and B are stable, C is meta-stable
© Digital Integrated Circuits2nd
Sequential Circuits
 Mux-Based Latches (now you see why
comb feedback is prohibited!!)
Negative latch Positive latch
(transparent when CLK= 0) (transparent when CLK= 1)

Q 0 Q
1

D 0 D 1

CLK CLK

Q  Clk  Q  Clk  In Q  Clk  Q  Clk  In

© Digital Integrated Circuits2nd

Sequential Circuits
 Writing into a Static Latch
Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK
CLK

Q D D
CLK
CLK
D

CLK
Forcing the state
Converting into a MUX (can implement as NMOS-only)

© Digital Integrated Circuits2nd

Sequential Circuits
 Mux-Based Latch
CLK

CLK

CLK

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Sequential Circuits
 Mux-Based Latch

CLK
QM
CLK

QM

CLK

CLK

NMOS only Non-overlapping clocks

© Digital Integrated Circuits2nd

Sequential Circuits
 QUIZ
Using dynamic logic family, implement the following
function:

F=a+bc+d

Then evaluate two scenarios:

1.b=c=d=0, a=1 for some time after CLK=1 and then
goes zero.
2.B=c=d=0, a=1 after CLK=1 and stay 1.

© Digital Integrated Circuits2nd

Sequential Circuits
 Master-Slave (Edge-Triggered)
Register
Slave
Master

0 Q D
1 QM
1
QM
D 0 Q

CLK
CLK

Two opposite latches trigger on edge

Also called master-slave latch pair

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Sequential Circuits
 Master-Slave Register
Multiplexer-based latch pair

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK

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Sequential Circuits
 Clk-Q Delay

2.5
CLK

1.5
Volts

D
tc 2 q(lh) tc 2 q(hl)
Q
0.5

2 0.5
0 0.5 1 1.5 2 2.5
time, nsec

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Sequential Circuits
 Setup Time
Picked up here Violated here
3.0 3.0
Q
2.5 2.5

2.0 QM 2.0 I2 2 T 2

1.5 1.5 Q
CLK CLK
Volts

Volts
D D
1.0 1.0
I2 2 T 2 QM
0.5 0.5

0.0 0.0

2 0.5 2 0.5
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
time (nsec) time (nsec)
(a) T setup 5 0.21 nsec (b) T setup 5 0.20 nsec

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Sequential Circuits
 Reduced Clock Load
Master-Slave Register

CLK CLK

D T1 I1 T2 I3 Q

I2 I4
CLK CLK

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Sequential Circuits
© Digital Integrated Circuits2nd
Sequential Circuits
 Overpowering the Feedback Loop ─
Cross-Coupled Pairs
NOR-based set-reset

S R Q Q
S
Q
S Q 0 0 Q Q
1 0 1 0
R Q
0 1 0 1
Q
R 1 1 0 0

Forbidden State

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Sequential Circuits
 Cross-Coupled NAND : QUIZ , give
me truth table !!!

Cross-coupled NANDs

S
Q

Q
R

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Sequential Circuits
 Storage Mechanisms

Static Dynamic (charge-based)

CLK
CLK

D Q
Q

CLK
CLK
D

CLK

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Sequential Circuits
 Other Latches/Registers: C2MOS
VDD VDD Assignment:

M2 M6 A C2MOS register
with CLK-CLK
CLK M4 CLK M8
X
clocking is
D Q insensitive to
CL1 CL2
CLK M3 CLK M7 overlap as
compared to TXR-
M1 M5 switch FF, as long
as the rise and
fall times of the
Master Stage
clock edges are
sufficiently small.
© Digital Integrated Circuits2nd
Sequential Circuits
 Other Latches/Registers: TSPC
VDD VDD VDD VDD

Out

In CLK CLK In CLK CLK

Positive latch Negative latch

(transparent when CLK= 1) (transparent when CLK= 0)

© Digital Integrated Circuits2nd

Sequential Circuits
 When CLK = 0, the input
inverter is sampling the
TSPC Register inverted D input on node X.
The second
(dynamic) inverter is in the
precharge mode, with M6
charging up node Y to VDD.
VDD VDD VDD The third
inverter is in the hold mode,
since M8 and M9 are off.
CLK Q Therefore, during the low
M3 M6 M9
phase of
Y the clock, the input to the final
Q
(static) inverter is holding its
D CLK X CLK previous value and the output
M2 M5 M8
Q is stable. On the rising
edge of the clock, the
dynamic inverter M4-M6
CLK evaluates. If X is
M1 M4 M7
high on the rising edge, node
Y discharges. The third
inverter M7-M8 is on during
the high
phase, and the node value on
Y is passed to the output Q.
© Digital Integrated Circuits2nd
Sequential Circuits
 Pulse-Triggered Latches
An Alternative Approach
Ways to design an edge-triggered sequential cell:

Master-Slave Pulse-Triggered
Latches Latch
L1 L2 L
Data Data
D Q D Q D Q

Clk Clk Clk Clk

Clk

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Sequential Circuits
 Transition-Triggered Monostable

In
DELAY
Out
td td

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Sequential Circuits
 Project

Design a positive edge triggered flip-flop that would

operate at 2GHz alone.

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Sequential Circuits