The Devices : Diode, MOSFET

 Present intuitive understanding of device

operation
 Introduction of basic device equations
 Introduction of models for manual
analysis
 Analysis of secondary and deep-sub-
micron effects

Any guesses , why diode is included and BJTs excluded?

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 The Diode
B Al A
SiO2

Cross-section of pn-junction in an IC process

A Al
p A

B B
One-dimensional
representation diode symbol

Mostly occurring as parasitic element in Digital ICs

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 Depletion Region & Barrier Potential
hole diffusion
electron diffusion
(a) Current flow.
p n

hole drift
electron drift
Charge 
Density
+ x (b) Charge density.
Distance
-

Electrical 
Field x (c) Electric field.

V
Potential
 (d) Electrostatic
x potential.
-W 1 W2

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 Diode Current : Static Behavior

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 Forward Bias

pn (W2)
pn0

Lp

np0

-W1 0 W2 x
p-region n-region

diffusion

Typically avoided in Digital ICs

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 Reverse Bias

pn0

np0

-W1 0 W2 x
p-region n-region

diffusion

The Dominant Operation Mode

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 Models for Manual Analysis

ID = IS(eV D/T – 1) ID
+ +
+
VD VD VDon
–
– –

(a) Ideal diode model (b) First-order diode model

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 Dynamic Behavior
Junction Capacitance

CJ0 is under zero bias

condition

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 Junction Capacitance with Bias Voltage

Why decreasing with

reverse bias?

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 Diodes : Secondary Effects
Strong Temperature Dependence
-VT is temperature dependent
0.1
-Is is temperature dependent

ID (A)
0

–0.1
–25.0 –15.0 –5.0 0 5.0
VD(V)

Avalanche Breakdown

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 Diode Model

RS

VD ID CD

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 What is a Transistor? Digital perspective
Any idea why we needed extra devices apart from R,L & C

A Switch! An MOS Transistor

VGS  VT |VGS|

R on
S D

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 The MOS Transistor
Polysilicon Aluminum

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MOS Transistors - Self-study : difference between
Types and Symbols these types

D D

G G

S S

NMOS Enhancement NMOS Depletion

D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact

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Threshold Voltage: Concept
+
S VGS D
G
-

n+ n+

n-channel Depletion
Region
p-substrate

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Assignment # 1 :
The Threshold Voltage

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 The Body Effect
0.9

0.85

0.8

0.75

0.7
VT (V)

0.65

0.6

0.55

0.5

0.45

0.4
-2.5 -2 -1.5 -1 -0.5 0
VBS (V)

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 Current-Voltage Relations
A good ol’ transistor
-4
x 10
6
VGS= 2.5 V

Resistive Saturation
4
VGS= 2.0 V
ID (A)

3 Quadratic
VDS = VGS - VT Relationship
2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

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Transistor in Linear
VGS VDS
S
G ID
D

n+ –
V(x)
+ n+

L x

p-substrate

MOS transistor and its bias conditions

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Transistor in Saturation
VGS

VDS > VGS - VT

G

D
S

- +
n+ VGS - VT n+

Pinch-off

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Current-Voltage Relations
Long-Channel Device

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A model for manual analysis

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 Current-Voltage Relations
The Deep-Submicron Era
-4
x 10
2.5

VGS= 2.5 V
Early Saturation
2

VGS= 2.0 V
1.5
ID (A)

Linear
1
VGS= 1.5 V Relationship

0.5 VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

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 Velocity Saturation
n (m/s)

5
sat
Constant velocity

Constant mobility (slope = µ)

c= 1.5 (V/µm)

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 Perspective
ID
Long-channel device

VGS= VDD
Short-channel device

VDSAT VGS- VT VDS

Extended saturation region due to velocity saturation

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 ID versus VGS
-4
x 10 x 10
-4
6 2.5

5
2

4 linear
quadratic 1.5
ID (A)

ID (A)
3

1
2

0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)

Long Channel Short Channel

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 ID versus VDS

-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V
VGS= 2.5 V
5
2
Resistive Saturation
4 VGS= 2.0 V
VGS= 2.0 V 1.5

ID(A)
ID(A)

3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V
0.5 VGS= 1.0 V
1
VGS= 1.0 V
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)

Long Channel Short Channel

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A unified model
for manual analysis

S D

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 A PMOS Transistor : SELF-STUDY
-4
x 10
0
VGS = -1.0V

-0.2
VGS = -1.5V

-0.4
ID (A)

VGS = -2.0V
-0.6 Assume all variables
negative!
-0.8
VGS = -2.5V

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)

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 Transistor Model
for Manual Analysis

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 Transistor as a Switch
VGS  VT
IDI
R on D VVGS ==VVD D
GS DD
S D
RRmid
mid

RR0
0

VVDS
DS
VVDD/2
DD/2
VVDD
DD

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 Transistor as a Switch
5
x 10
7

5
Req (Ohm)

0
0.5 1 1.5 2 2.5
VDD (V)

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 Transistor as a Switch

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Dynamic Behavior of MOS Transistor : MOS
Capacitances
G

CGS CGD

S D

CSB CGB CDB

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 The Gate Capacitance
Polysilicon gate

Source Drain
W
n+ xd xd n+

Gate-bulk
Ld
overlap
Top view
Gate oxide
tox
n+ L n+

Cross section

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 Gate Capacitance
G G G

CGC CGC CGC

S D S D S D

Cut-off Resistive Saturation

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Gate Capacitance

CG C
WLC ox

WLC ox C G CS = CG CD
CGC B
2

VG S

Capacitance as a function of VGS

(with VDS = 0)

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 Diffusion Capacitance
Channel-stop implant
NA 1

Side wall
Source
W
ND

Bottom

xj Side wall
Channel
LS Substrate N A

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 Capacitances in 0.25 m CMOS
process

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The Sub-Micron MOS Transistor
 Threshold Variations
 Subthreshold Conduction
 Parasitic Resistances

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 Threshold Variations

VT VT

Long-channel threshold Low VDS threshold

VDS
L

Threshold as a function of Drain-induced barrier lowering

the length (for low VDS ) (for low L)

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 Sub-Threshold Conduction
-2
10

Linear qVGS
-4
10
I D ~ I 0e nkT

-6
10 Quadratic
ID (A)

-8
10

-10 Exponential
10

-12 VT
10
0 0.5 1 1.5 2 2.5
VGS(V)

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 Summary of MOSFET Operating
Regions
 Strong Inversion VGS > VT
 Linear (Resistive) VDS < VDSAT
 Saturated (Constant Current) VDS  VDSAT
 Weak Inversion (Sub-Threshold) VGS  VT
 Exponential in VGS with linear VDS dependence

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 Parasitic Resistances

Polysilicon gate
Drain
contact
G LD

VGS,eff

W
S D

RS RD

Drain

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