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Basic Computer OrganizationMemory Reference Instructions

This document discusses memory reference instructions in a computer system. It describes 7 different memory reference instructions - AND, ADD, LDA, STA, BUN, BSA, and ISZ. For each instruction, it explains the operation code, what the instruction does, and the timing of retrieving data from memory and executing the instruction. It includes a flow chart that visually shows the process for each memory reference instruction.

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HARI HARAN REDDY
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14 views9 pages

Basic Computer OrganizationMemory Reference Instructions

This document discusses memory reference instructions in a computer system. It describes 7 different memory reference instructions - AND, ADD, LDA, STA, BUN, BSA, and ISZ. For each instruction, it explains the operation code, what the instruction does, and the timing of retrieving data from memory and executing the instruction. It includes a flow chart that visually shows the process for each memory reference instruction.

Uploaded by

HARI HARAN REDDY
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Basic Computer Organization

Memory Reference Instructions

Computer Organization and Design


Agenda
 Instruction Codes

 Computer Registers

 Common Bus System

 Computer Instructions

 Timing and Control

 Instruction Cycle

 Memory Reference Instructions

 Input-Output and Interrupt

 Complete Computer Description


Memory Reference Instructions
Memory Reference Instructions
Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
1. AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC

2. ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC & store carry in
E

3. LDA: Load to AC
D2T4: DR  M[AR] Read operand
D2T5: AC  DR, SC  0 Transfer data from
AR to AC

4. STA: Store AC
D3T4: M[AR]  AC, SC  0 Store the value of AC in the
Memory
Memory Reference Instructions

5. BUN: Branch Unconditionally


D4T4: PC  AR, SC  0

6. BSA: Branch and Save Return Address


D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135


Memory Reference Instructions

7. ISZ: Increment and Skip-if-Zero


D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
Flow Chart - Memory Reference Instructions
Memory-reference instruction

AND ADD LDA STA

D0T 4 D1T 4 D2T 4 D 3T 4

DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC


SC  0

D0T 5 D1T 5 D2T 5


AC  AC DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4T 4 D5T 4 D6T 4


PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5T 5 D6T 5

PC  AR DR  DR + 1
SC  0
D6T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
Thank You!

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