Advanced Digital System

Design
Unit – 3 Fault Diagnosis and Testability Algorithms
D ALGORTIHM

Keerthana S – 2023203032
M.E Applied Electronics
Introduction
• The size of circuits is growing, the complexity of test pattern generation also
increases.
• Hence manual test generation (being too cumbersome) is not a feasible method
anymore.
• Therefore, we need the help of automatic test pattern generation (ATPG).
• But methods studied earlier in this DFT course like the path sensitization
method is a very intuitive approach and can’t be developed into an algorithm
for computer software.
WHAT IS DFT and ATPG?
• Design for Testability (DFT) in Very Large Scale Integration (VLSI) refers to the practice
of designing integrated circuits (ICs) with testability features built into the hardware
architecture. The goal of DFT is to make it easier and more efficient to test and diagnose
faults in the manufactured chips.
• Test pattern generation (TPG) is the process of generating test patterns for a given fault
model. If we go by exhaustive testing, in the worst case, we may require
2n (where n stands for no. of primary inputs) assignments to be applied for finding test
vector for a single stuck-at fault. It is impossible for us to manually use exhaustive testing
or path sensitization method to generate a test pattern for chips consisting of millions of
transistors. Hence, we need an automated process- Automatic Test Pattern Generation
(ATPG).
• ATPG - Automatic Test Pattern Generation, or ATPG, is a process used in
semiconductor electronic device testing wherein the test patterns required to check a
device for faults are automatically generated by a program.
ATPG Classification
Based on Algorithm

Complete ATPG Incomplete ATPG

Based on Application
• As we have frequently noticed in this DFT course, DFT techniques
and test generation become significantly tricky for sequential circuits
as compared to combinational circuits.
• This is due to controllability and observability issues in internal flip-
flops and latches.
• Hence, the ATPG algorithms are applied separately for combinational
and sequential circuits.
• The ATPG algorithm is broadly classified into two types:
1.Combinational ATPG (e.g. D, PODEM, FAN)
2.Sequential ATPG (e.g. Extended D, 9-valued)
D Algorithm
• The D algorithm was developed by Roth at IBM in 1966 and was the
first complete test pattern algorithm designed to be programmable on a
computer.
• The D algorithm is a deterministic ATPG method for combinational
circuits, guaranteed to find a test vector if one exists for detecting a
fault. It uses cubical algebra for the automatic generation of tests.
• Three types of cubes are considered:
1. Singular cube
2. Propagation D-cube (PDC)
3. Primitive D-cube of a fault (PDCF)
THE D- ALGEBRA
• The D-algebra is a 5-value logic consisting of logic: 1, 0, D, D', X. The D stands for
Discrepancy

• The algebraic rules applicable in D algorithm for intersection:

• 0∩0=0∩x=x∩0=0
• 1∩1=1∩x=x∩1=1
• x∩x=x
• 1∩0=D
• 0 ∩ 1 = D’
CUBES
1.Singular Cover
• Singular Cover (SC) of any logic gate is the compact form of truth-table. This is done
using don’t cares (x). Following reduced truth table is the singular cover of an AND gate.
• Each row of a singular cover is termed as Singular Cube. The below singular cover of
the AND gate has three singular cubes.
2.Primitive D-cube of a Fault
• D-cubes represent the input-output behavior of the good and faulty circuits.
• Primitive D-cube of a Fault (PDCF) is used to specify the minimum input conditions required at
inputs of a gate to produce an error at its output. This is used for fault activation. PDCF can be
derived from the intersection of singular covers of gates in faulty and non-faulty conditions having
different outputs.
• Example:
• Here is an AND gate with s-a-0 fault at the output. To generate the PDCF, we first draw the truth
table of the faulty and non-faulty circuit. Next, we derive the singular cover for faulty as well as
non-faulty circuits.
3.Propagation D-cube
• Propagation D-cubes (PDCs) of a gate causes the output of the gate to depend upon the
minimum number of its specified inputs. It is used to propagate D or D’ from a specified
input to the output. Propagation D-Cubes can be derived from the intersection of singular
cubes of gates of opposite output values.
• Example:
• Here’s the truth table of an OR gate. To generate the PDC, we find the singular cover for
the OR gate.
FRONTIERS
• In the D algorithm, we have two essential components:
• D-frontier: A set of gates whose output value is currently unknown, but have one
or more D (or D’) at their inputs.
• J-frontier: A set of gates whose output value is assigned, but input values have not
been decided yet.
• The blue gates are D-frontier while green gates are J-frontier.
TEST CUBES
• A test cube represents partially specified signal values at various nodes
in the circuit during each step of the test generation process. Test cubes
contain primary inputs as well as internal nodes.
• A test cube at ATPG step n is denoted by TC(n).
• Intersection of Test Cubes
• After every successive step in ATPG, we need to intersect test-cubes
to obtain the unified test cube.
• In this intersection, two bits can be only intersected if their logic values
are not conflicting.
IMPLICATIONS
• Implication in D algorithm means determining unknown values in
input/output wires with a known set of values. Implication is done any time a
decision is made.
• Forward Implication: Uniquely determining the output values from partially
(or fully) specified input values of a gate.
• Backward Implication: Uniquely determining the un-specified input
values from the specified output values (and some input values) of a
gate.
EXAMPLE
The test generation process consists of the following three steps:
• Step 1: Generate a PDCF for the given fault. In this way, we create D-frontier.
This is also known as fault activation.
• Step 2: Drive the D (or D’) from the output of the gate under test to an output of
the circuit by successively intersecting the current test cube with the propagation
D-cubes of successive gates. The intersection of a test cube with the propagation
D-cube of a successor gate results in another test cube. This process is also known
as D-drive or forward propagation.
• Step 3: Justify the internal line values by driving back towards the inputs of the
circuit, assigning input values to the gates so that a consistent set of circuit input
values may be obtained. This process is known as justification of J-
frontiers or backpropagation.
• Step 4: Backtrack to previous steps if any conflict occurs in justification.
PROCEDURE
• Demonstrate the application of the D algorithm by deriving a test for detecting the g→s-
a-0 fault in the following circuit.
Step 1: Activate the fault by using PDCF of AND gate with output s-a-0 for gate G1.
Discrepancy D is generated.
Step 2: Forward propagate D by using suitable PDC of OR gate G3. For OR gate we have
PDCs as: {0, D/D’, D/D’}, {D/D’, 0, D/D’} and {D/D’, D/D’, D/D’}. Since already one of
its input (g) is assigned D, we chose PDC as {D, 0, D}. There is only one single D-
frontier in this case.
Step 3: Intersect test cubes of row 1 and row 2 to obtain the unified test cube. Follow the
test-cube intersection table for this. Empty boxes can be assumed as don’t care (x).
• TC(1) = TC(0) ∩ PDG3 = {1, 1, x, x, x, x, D, x, x, x, x, x} ∩ { x, x, x, x, x, x, D, 0, x, D, x,
x, x}
• = {1∩x, 1∩x, x∩x, x∩x, x∩x, x∩x, D∩D, x∩0, x∩x, x∩D, x∩x, x∩x, x∩x}
• = {1, 1, x, x, x, x, D, 0, x, D, x, x, x}
• Now we can D-drive through gate G3 towards the next D-frontiers.
Step 4: After every forward propagation, we need to perform backward implication to
satisfy the J-frontier and check for consistency. For this, first, obtain the singular cover
of NAND gate G2. Since its output is already assigned logic-0, the only possible singular
cover is {1, 1, 0}.
Step 5: Intersect test cubes to obtain the unified test cube. J-frontier is satisfied, and
consistency is maintained.
Step 6: For forward propagation, there are two possible D-frontiers available,
gate G5 and G6. We chose the gate G5.
Step 7: Find PDC of AND gate G5 for forward propagation.
Step 8: D-drive through gate G5 by intersecting the previous two test-cubes. We have finally
reached the primary outputs.
Step 9: Perform backward implication to justify the J-frontier gate G4. For this, we again
need to find a suitable singular cover.
Step 10: Intersect last two test-cubes to obtain the final test-cube. No conflicts during
intersection, hence justification completed. Assign don’t care (x) to the remaining empty
boxes like f and y to obtain the complete test-cube.
• The test vector for finding the g→s-a-0 fault is:
• {a, b, c, d, e, f} = {1, 1, 1, 1, x, x}
Advantage:
• D algorithm is a complete ATPG algorithm ; hence it guarantees to
generate a pattern for a testable fault.
Disadvantages:
• All the internal signals need to be assigned in the D algorithm, thus it
has a huge search space. Therefore, it is a time-consuming and slow
algorithm.
• Backtracking is required for consistency checks. Backtracking
becomes much more difficult, especially for reconvergent fanout
circuits.
CONCLUSION
• In this article, we studied one of the very first algorithms for combinational ATPG, i.e., D
algorithm.
• The D algorithm uses a cubical algebra containing singular cover, propagation D-cubes,
and primitive D-cubes.
• The intersection of these cubes with each other yields a test cube. The test cubes represent
the partial values of wires assigned during the algorithm.
• At each progressive step, the previous test cubes need to be intersected with newer test
cube.
• The D algorithm is all about moving the D-frontier forward towards the primary output
(forward propagation or D-drive) while moving the J-frontier backward until we reach the
primary inputs (backpropagation or justification).
REFERENCES
• D algorithm - Combinational ATPG in DFT (VLSI) (technobyte.org)
• FAULT TOLERANT AND FAULT TESTABLE HARDWARE
DESIGN -- PARAG K_LALA -- Englewood Cliffs, N_J, New Jersey
• D-Algorithm – Research Gate
THANK YOU