COE 372 Sem2, 2022/23

Introduction to VHDL
 Reading
• P. Chu, FPGA Prototyping by VHDL
Examples
– Chapter 1, Gate-level combinational circuits
• Xilinx XST User Guide
– Xilinx specific language support

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 Lecture Overview
• VHDL Fundamentals
• Describing Designs
• Libraries
• STD_Logic
• Modeling Styles
• Dataflow Modeling
• Structural Modeling
• Behavioral Modeling
• Verification and Test Bench
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 VHDL
• VHDL is a language for describing digital logic
systems used by industry worldwide
• VHDL is an acronym for VHSIC (Very High
Speed Integrated Circuit) Hardware Description
Language
• Now, there are extensions to describe analog
designs.

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 Versions of VHDL
• IEEE-1076 1987
• IEEE-1076 1993 ← most commonly supported by CAD
tools
• IEEE-1076 2000 (minor changes)
• IEEE-1076 2002 (minor changes)
• IEEE-1076 2008

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VHDL FUNDAMENTALS

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 Naming and Labeling (1)
• VHDL is case insensitive.
– Example of a name or label
• databus
• Databus
• DataBus
• DATABUS
– are all equivalent
• Avoid inconsistent styles

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 Naming and Labeling (2)
General rules of thumb (according to VHDL-87)
1. All names should start with an alphabet character (a-z or A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9) and
underscore (_)
3. Do not use any punctuation or reserved characters within a
name (!, ?, ., &, +, -, etc.)
4. Do not use two or more consecutive underscore characters (_
_) within a name (e.g., Sel_ _A is invalid)
5. No forward slashes “/” in names.
6. All names and labels in a given entity and architecture must
be unique.

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 Extended Identifiers
• Allowed only in VHDL-93 and higher:
1. Enclosed in backslashes
2. May contain spaces and consecutive underscores
3. May contain punctuation and reserved characters within a name
(!, ?, ., &, +, -, etc.)
4. VHDL keywords allowed
5. Case sensitive
• Examples:
\rdy\ \My design\ \!a\
\RDY\ \my design\ \-a\
• Should not be used to avoid confusioin!

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 Literals
• Numeric: 32, -16, 3.1415927
• Bits : ‘1’, ‘0’
• Strings: “Hello”
• Bit strings: B”1111_1111”, O”353”, X”AA55”
• Concatenation: “1111” & “0000” => “1111_0000”

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 Objects
• Signal – model real physical wires for communications
– Or physical storage of information
• Variable – a programming construct to model temporary
storage
• Constant – its value never changes after initialization

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 Comments (1)
• Comments in VHDL are indicated with a “double dash”,
i.e., “--”
– Comment indicator can be placed anywhere in the line
– Any text that follows in the same line is treated as a comment
– Carriage return terminates a comment
– No method for commenting a block extending over a couple of
lines
• Examples:
-- main subcircuit
Data_in <= Data_bus; -- reading data from the input FIFO

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 Comments (2)
• Explain function of module to other designers
• Explanatory, not Just restatement of code
• Placed close to the code described
– Put near executable code, not just in a header

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 Free Format
• VHDL is a “free format” language
– No formatting conventions, such as spacing or indentation
imposed by VHDL compilers. Space, tabs, and carriage return
treated the same way.
• Example:
if (a=b) then
or
if (a=b) then
or
if (a =
b) then
are all equivalent
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DESCRIBING DESIGNS

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 Example: NAND Gate
Design name
and
Interface

entity nand_gate is
port( a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC);
end nand_gate;
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 Example: NAND Gate –
Function

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;
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 Example VHDL Code
• 3 sections of VHDL code to describe a design.
• File extension for a VHDL file is .vhd
• Name of the file should be the same as the entity name
(nand_gate.vhd)

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 Design Entity

• Design Entity - most basic

building block of a design.

• One entity can have many

different architectures.

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 Entity Declaration
• Entity Declaration describes an interface of the
component, i.e. input and output ports.

Semicolon
after closing parenthesis

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 Entity Declaration –
Simplified Syntax
ENTITY entity_name IS
PORT (
port_name : port_mode signal_type;
port_name : port_mode signal_type;
………….
port_name : port_mode signal_type
);
END ENTITY entity_name;

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 Port Mode – IN

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 Port Mode – OUT

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Port Mode – OUT (with Extra Signal)

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 Port Mode – INOUT

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 Port Modes – Summary
• The Port Mode of the interface describes the direction in
which data travels with respect to the component
– In: Data comes into this port and can only be read
within the entity. It can appear only on the right side
of a signal or variable assignment.
– Out: The value of an output port can only be updated within the
entity. It cannot be read. It can only appear on the left side of
a signal assignment.
– Inout: The value of a bi-directional port can be read and
updated within the entity model. It can appear on both sides of
a signal assignment.

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 Architecture (Architecture body)
• Describes an implementation of a design entity
• Architecture example:

• Logic operators:
– NOT, AND, OR, NAND, NOR, XOR, XNOR

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Architecture – Simplified Syntax

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 Entity Declaration & Architecture

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 Tips & Hints (1)
• Place each entity in a different file.
• The name of each file should be exactly the same
as the name of an entity it contains.

• These rules are not enforced by all tools but are

worth following in order to increase readability
and portability of your designs

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 Tips & Hints (2)
• Place the declaration of each port, signal,
constant, and variable in a separate line for better
readability

• These rules are not enforced by all tools but are

worth following in order to increase readability
and portability of your designs

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LIBRARIES

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 Library Declarations

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 Library Declarations – Syntax

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 Structure of a Library

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 Libraries

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 Operators in Standard VHDL

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 Standard VHDL – Data Types
• integer
– Minimal range: -(2^31 – 1) to 2^31 – 1
• boolean: {true, false}
• bit: {‘1’, ‘0’}
• bit_vector: string of bits.
– “0001_1111”

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STD_LOGIC DEMYSTIFIED

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 Operators in Standard VHDL

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 STD_LOGIC

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 BIT versus STD_LOGIC
• VHDL standard BIT type
– Can only model a value of ‘0’ or ‘1’

• STD_LOGIC can model nine values

– ’U’, ’X’, ‘0’, ’1’, ’Z’, ’W’, ’L’, ’H’, ’-’
– Useful mainly for simulation
– ‘0’, ’1’, ‘X’ and ‘Z’ are synthesizable
(your codes should use only these four values)

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 STD_LOGIC type demystified

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 STD_LOGIC Meanings (1)

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 STD_LOGIC Meanings (2)

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 Resolving Logic Levels

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 STD_LOGIC Rules
• In this course, use only std_logic or std_logic_vector
for all entity input or output ports
• Do NOT use integer, unsigned, signed, bit for ports
– You can use them inside of architectures if desired
– You can use them in generics
• Instead use std_logic_vector and a conversion function
inside of your architecture

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 Signals Modeling Wires and Buses
SIGNAL a : STD_LOGIC;

SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

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 Standard Logic Vectors

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 Vectors and Concatenation

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 Merging Wires and Buses

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 Splitting Buses

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MODELING STYLES

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 Design Entity

• Design Entity - most basic

building block of a design.

• One entity can have many

different architectures.

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 Types of VHDL Descriptions

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 xor3 Example

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 Entity xor3 Gate

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY xor3 IS
PORT( A : IN STD_LOGIC;
B: IN STD_LOGIC;
C: IN STD_LOGIC;
Result : OUT STD_LOGIC);
end ENTITY xor3;

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DATAFLOW MODELING

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 Dataflow Architecture - xor3 Gate

ARCHITECTURE dataflow OF xor3 IS

SIGNAL U1_OUT: STD_LOGIC;
BEGIN
U1_OUT <= A XOR B;
Result <= U1_OUT XOR C;
END ARCHITECTURE dataflow;

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 Dataflow Description
• Describes how data moves through the various processing steps
of the system.
– Uses series of concurrent statements to realize logic.
• Most useful style when series of Boolean equations can represent
a logic  used to implement simple combinational logic
– Dataflow code also called concurrent code
• Concurrent statements are evaluated at the same time; thus, the
order of these statements does NOT matter
– This is not true for sequential/behavioral statements

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 Event-Driven Semantics (1)
• When a concurrent statement is evaluated?

when there is an event on a signal on the

right hand side of an assignment.

• An event is a change of value on a signal.

• Consider the example in the previous slide.

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 Event-Driven Semantics (2)

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 Event-Driven Semantics (3)

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 Event-Driven Semantics (4)

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 Event-Driven Semantics (5)

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 Event-Driven Semantics
Another Example (1)

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 Event-Driven Semantics
Another Example (2)

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 Event-Driven Semantics
Another Example (3)

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STRUCTURAL MODELING

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Structural Architecture – xor3 Gate

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 Structural Architecture in VHDL 93

ARCHITECTURE structural OF xor3 IS

SIGNAL U1_OUT: STD_LOGIC;
BEGIN
U1: entity work.xor2(dataflow) –- VHDL93 style
PORT MAP (I1 => A, I2 => B, Y => U1_OUT);
U2: entity work.xor2(dataflow)
PORT MAP (I1 => U1_OUT, I2 => C, Y => Result);
END ARCHITECTURE structural;
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 Structural Architecture in VHDL 93
General Syntax

inst_label: entity lib_name.entity_name(arch_name)

PORT MAP (
port1 => actual_signal1,
port2 => actual_signal2,
...
);

Actual signals can be

• ports of the entity where the component is instantiated
• signals declared in the architecture body

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 Structural Architecture in VHDL 87
ARCHITECTURE structural OF xor3 IS
SIGNAL U1_OUT: STD_LOGIC;
COMPONENT xor2
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;

BEGIN
U1: xor2 PORT MAP (I1 => A, I2 => B, Y=> U1_OUT);
U2: xor2 PORT MAP (I1 => U1_OUT,
I2 => C,
Y => Result);
END05.2023
structural; 73
 Structural Description
• Allows divide-n-conquer for large designs.
• This style is the closest to schematic capture and utilizes
simple building blocks to compose logic functions.
• Components are interconnected in a hierarchical
manner.
• Structural descriptions may connect simple gates or
complex, abstract components.
• Structural style is useful when expressing a design that
is naturally composed of sub-blocks.

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BEHAVIORAL MODELING

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 Behavioral Architecture – xor3 Gate
ARCHITECTURE behavioral OF xor3 IS
BEGIN
xor3_behave: PROCESS (A, B, C)
BEGIN
IF ((A XOR B XOR C) = '1') THEN
Result <= '1';
ELSE
Result <= '0';
END IF;
END PROCESS xor3_behave;
END ARCHITECTURE behavioral;

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 Behavioral Description
• It describes what happens on the inputs and outputs of
the black box (no matter how a design is actually
implemented).
– Focus on functions mapping inputs to outputs
– Similar to dataflow style,
– More like sequential SW programming.
• This style uses process statements in VHDL.
– A process itself is a concurrent statement.
– A process consist of sequential statements.
• More later.

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VERIFICATION AND TEST
BENCH
05.2023 78
 Design Testing and Testbenches
• After a design is done, it needs to be tested.
• During testing, design inputs are driven by various test
vectors, and
• Outputs are monitored and checked.

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 Testbench in VHDL

library ieee;
use ieee.std_logic_1164.all;

ENTITY testbench IS
END testbench;
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