COE 372 Sem2, 2022/23

VHDL Processes and

Sequential Statements
Modeling Combinational
Circuits
 Lecture Overview
• Process as a Concurrent Statement
• Anatomy of a Process
• Sequential Statements
• Sensitivity List
• Process Semantics
• Processes Modeling Combinational Circuits
• Sequential Statement: wait
• Conditional Concurrent Signal Assignments
• Selected Concurrent Signal Assignments
• Selected Concurrent Signal Assignments: case
05.2023 2
 Process Statements
• A processes is a concurrent statement.
• Processes describe combinational/sequential
behavior
• Processes in VHDL are very powerful statements
– Allow to define arbitrary behavior that may be
difficult to represent by a real circuit
– Not every process can be synthesized
• Use processes with caution in order to write the
synthesizable code.
• Use processes freely in testbenches for
05.2023 3
simulation.
 Concurrent Statements
• ➜ simple concurrent signal assignment
( <=)

• ➜ conditional concurrent signal assignment

(when-else)

• ➜ selected concurrent signal assignment

(with-select-when)

• ➜ Processes
05.2023 4
 Anatomy of a Process

[label:] process [(sensitivity list)]

[declaration part]
begin
sequential statements
end process [label];
05.2023 5
 Sequential Statements
• Used only in processes
• Evaluated one at a time sequentially
• Include
– Signal/variable assignments
– IF statements
– CASE statements
– WAIT statements
– Other – loop, …

05.2023 6
 PROCESS with a SENSITIVITY
LIST
• List of signals to which
the process is sensitive.
• Whenever there is an
event on any of thesignals
in the sensitivity list, the
process fires. label:
• Every time the process process (sensitivity list)
fires, it will run in its declarations
entirety.
begin
sequential statements
end process;

05.2023
wait statements are NOT ALLOWED in a process 7
with a sensitivity list.
 Processes – Semantics
1. An event on a sensitive signal occurs, or
2. Certain amount of delay has passed.

3. Finish sequential execution, or

4. encounter wait
05.2023 8
 Processes Modeling
Combinational Circuits (1)
priority: process(a, b)
begin
c <= a and b;
end process;

To model a combinational circuit, all input signals

and signals on RHS of signal assignments must be
included in the sensitivity list!
05.2023 9
 Processes Modeling
Combinational Circuits (2)
priority: process
begin
-- sensitivity list not used
-- wait statement
wait on a, b;
c <= a and b;
end process;
To model a combinational circuit, all input signals and signals on
RHS of signal assignments must be included in the sensitivity list!

05.2023 10
 Wrong Processes
priority: process(a, b)
begin
wait on a, b;
c <= a and b;
end process;

wait statements are NOT ALLOWED in a process with a

sensitivity list.
05.2023 11
 Sequential Statement: wait
wait until boolean_condition;
-- wait until a=‘1’ and b=‘0’;

wait on signal_list;
-- wait on a, b;

wait for time;

-- wait for 10 ns;

wait; -- suspend the process forever

Synthesis – Do not use WAIT when modeling a design.
05.2023 12
 Process for Conditional
Concurrent Signal Assignment
architecture arch of ex is
begin
r <= a + b + c when m=n else
a–b when m>0 else
c + 1;
end architecture arch;

05.2023 13
 Process for Conditional Concurrent Signal
Assignment – IF Statement
architecture arch of ex is
To model a combinational
begin circuit, all input signals, all
process(a, b, c, m, n) signals in conditions and
signals on RHS of signal
begin assignments must be included
if m=n then in the sensitivity list!
r <= a + b + c;
elsif m > 0 then
r <= a – b;
else
r <= c + 1;
end if;
end process;
05.2023 end architecture arch; 14
 If Statement – Syntax
if boolean_expr_1 then
sequential_statements;
elsif boolean_expr_2 then
sequential_statements;
elsif boolean_expr_3 then
sequential_statements;
...
else
sequential_statements;
end if;
05.2023 15
 Process for Selected Concurrent Signal
Assignment
architecture arch of ex is
begin
with sel select
r <= a + b + c when “00” else
a – b when “10” else
c + 1 when others;
end architecture arch;

05.2023 16
 Process for Selected Concurrent Signal
Assignment – Case Statement
architecture arch of ex is
begin
process(a, b, c, sel)
begin
case sel is
when “00” =>
r <= a + b + c;
when “10” =>
r <= a – b;
when others =>
r <= c + 1;
end case;
end process;
end architecture arch;
05.2023 17
 Case Statement – Syntax

case case_expression is
when choice_1 =>
sequential statements;
when choice_2 =>
sequential statements;
...
when choice_n =>
sequential statements;
end case;
05.2023 18
 Comparison to Concurrent Statements

large <= a when a > b else b;

small <= b when a > b else a;
process(a, b)
begin
if a > b then
large <= a;
small < = b;
else
large <= b;
small <= a;
end if;
05.2023
end process; 19
 Unintended Memory
process(a)
begin Implicit memory is
if a > b then introduced to hold gt
gt <= ‘1’; and eq.
elsif a = b then
eq <= ‘1’;
end if;
end process;
To model a combinational circuit,
1. all input signals,
2. all signals in conditions and
3. signals on RHS of signal assignments
05.2023
must be included in the sensitivity list! 20
 Avoid Unintended Memory
process(a, b)
begin
if a > b then
1. All input signals,
gt <= ‘1’; 2. all signals in conditions and
eq <= ‘0’ 3. signals on RHS of signal
elsif a = b then must be included in the sensitivity
gt <= ‘0’; list!
eq <= ‘1’;
else
gt <= ‘0’;
4. A signal must be assigned in
eq <= ‘0’; every branch.
end if;
end process;

05.2023 21
 Signal Assignments in Processes (1)

-- Is this process the

-- right model?
process (d1, d2, d3)
begin
s <= d1 xor d2;
o <= s and d3;
end process;

05.2023 22
 Signal Assignments in Processes (2)
-- Is this process the
-- right model?
process (d1, d2, d3)
begin
s <= d1 xor d2;
o <= s and d3;
end process;

05.2023 23
 Signal Assignments in Processes (3)
-- Is this process the
-- right model?
process (d1, d2, d3, s)
begin
s <= d1 xor d2;
o <= s and d3;
end process;

05.2023 24
 Signal Assignments in Processes (4)
process (d1, d2, d3, s)
begin
s <= d1 xor d2; process (d1, d2, d3, s)
o <= s and d3; begin
end process; o <= s and d3;
s <= d1 xor d2;
end process;

05.2023 25