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Lecture 10

leakage power

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21 views19 pages

Lecture 10

leakage power

Uploaded by

usagoer5
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EE466: VLSI Design

Power Dissipation
Outline

• Motivation to estimate power dissipation


• Sources of power dissipation
• Dynamic power dissipation
• Static power dissipation
• Metrics
• Conclusion
Need to estimate power dissipation

Power dissipation affects


• Performance
• Reliability
• Packaging
• Cost
• Portability
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors

• Short Circuit Currents


Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors
Node Transition Activity and Power
•Due to charging and discharging of capacitance

Consider switching a CMOS gate for N clock cycles


E = C  V 2  n N 
N L dd
EN : the energy consumed for N clock cycles
n(N): the number of 0->1 transition in N clock cycles
EN  n N  2
P avg = lim --------  fclk =  lim ------------   C  Vdd  f clk
N  N N  N L
N 
  = lim n
------------
0 1 N  N

P =   C V 2f
av g 0 1 L dd clk
Activity factors of basic gates
• AND  (1  p A p B ) p A p B

 (1  p A )(1  p B )[1  (1  p A )(1  p B )]


• OR

 [1  ( p A  p B  2 p A p B )]( p A  p B  2 p A p B )
• XOR
Dynamic Power dissipation

• Power reduced by reducing Vdd, f, C and also activity


• A signal transition can be classified into two categories
 a functional transition and
 a glitch
Glitch Power Dissipation

• Glitches are temporary changes in the value of the


output – unnecessary transitions
• They are caused due to the skew in the input signals to a
gate
• Glitch power dissipation accounts for 15% – 20 % of the
global power
• Basic contributes of hazards to power dissipation are
– Hazard generation
– Hazard propagation
Glitch Power Dissipation

• P = 1/2 .CL.Vdd . (Vdd – Vmin) ;


Vmin : min voltage swing at the output
• Glitch power dissipation is dependent on
– Output load
– Input pattern
– Input slope
Glitch Power Dissipation

• Hazard generation can be reduced by gate sizing and


path balancing techniques
• Hazard propagation can be reduced by using less
number of inverters which tend to amplify and
propagate glitches
Short Circuit Power Dissipation

• Short circuit current occurs during signal transitions


when both the NMOS and PMOS are ON and there is a
direct path between Vdd and GND
• Also called crowbar current
• Accounts for more than 20% of total power dissipation
• As clock frequency increases transitions increase
consequently short circuit power dissipation increases
• Can be reduced :
– faster input and slower output
– Vdd <= Vtn + |Vtp|
• So both NMOS and PMOS are not on at the same time
Static Power Consumption
Vdd

Istat
Vout

CL
Vin=5V

Pstat = P(In=1).Vdd . Istat

• Dominates over dynamic consumption


Wasted energy …
• Not a function of switching frequency
Should be avoided in almost all cases
Static Power Dissipation
• Power dissipation occurring when device is in standby
mode
• As technology scales this becomes significant
• Leakage power dissipation
• Components:
– Reverse biased p-n junction
– Sub threshold leakage
– DIBL leakage
– Channel punch through
– GIDL Leakage
– Narrow width effect
– Oxide leakage
– Hot carrier tunneling effect
Principles for Power Reduction
• Prime choice: Reduce voltage!
– Recent years have seen an acceleration in
supply voltage reduction
– Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)
• Reduce switching activity
• Reduce physical capacitance
– Device Sizing
Factors affecting leakage power

• Temperature
– Sub-threshold current increases exponentially
• Reduction in Vt
• Increase in thermal voltage
– BTBT increases due to band gap narrowing
– Gate leakage is insensitive to temperature change
Factors affecting leakage power

• Gate oxide thickness


– Sub-threshold current decreases in long channel transistors and
increases in short channel
– BTBT is insensitive
– Gate leakage increases as thickness reduces
Solutions

• MTCMOS
• Dual Vt
• Dual Vt domino logic
• Adaptive Body Bias
• Transistor stacking
Metrics

• Power Delay product


• Energy Delay Product
– Average energy per instruction x average inter
instruction delay
• Cunit_area
– Capacitance per unit area
Conclusion
• Power dissipation is unavoidable especially as
technology scales down
• Techniques must be devised to reduce power dissipation
• Techniques must be devised to accurately estimate the
power dissipation
• Estimation and modeling of the sources of power
dissipation for simulation purposes

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