RTL2GDS

Digital IC Design Flows

Dina Tantawy
Training Plan
• M.1: • M.5:
• Motivation . • Placement .
• Different Design Flows (FPGA vs ASIC). • Clock Tree Synthesis.
• Logic Synthesis. • M.6:
• Clock Tree Synthesis continue.
• M.2: • Routing.
• Static Time Analysis & SDC. • M.7:
• M.3: • Physical Verification: DRC
• Dynamic Time analysis & Utility • Physical Verification: LVS
scripting (TCL). • Physical Verification: PEX

• M.4:
• Design For testability.
• Floor Planning & Power Planning.
2
Agenda
Static Timing Analysis (STA)
Timing paths
FF operation and requirements
Design Objects [for all Synopsys tools]
Design Constraints

3
Slides adapted from
eng. Islam ahmed,
eng. Hossam hassan
Basics of Static Timing analysis
• Static Timing Analysis (STA) is a method for determining if a circuit meets timing
constraints without having to simulate.
• Simulation (dynamic analysis) circuit response for a specified set of input
patterns.

• STA is used to:

Validates if the design can operate at the set timing constraints. [reports timing
violations]
Is a complete and exhaustive verification of all timing checks of a design.
Is used instead of simulation.

5
Basics of Static Timing analysis
SC Derates
C onstrai .SPE Gatelevel netlist and
.lib
nts F (.v) Uncertaini
s
tes

Static Timing
A nalysis (PT)

Timing SDF
reports files

6
 Static Timing Analysis Gatelevel Timing Simulation
Usage •check timing requirements: setup, hold, recovery, •Functional and timing simulation,
removal, Logical DRCs.
•checking functionality by comparing output VS
•Much faster than timing-driven expected output.
simulation.
•More accurate
•Exhaustive, checks every possible
constrained timing path. •Can catch issues like glitches.

•No vector generation is required.

•The signal at the input is propagated through
the
gates at each level till it reaches the
output
Limitations •Only useful for synchronous digital circuits, can’t •Analysis quality can be dependent on stimulus
analyze asynchronous systems vectors
•Less accurate •Takes a lot if time and computational power.
•Must define timing requirements, false paths..etc. •Non-exhaustive.
Required inputs gatelevel netlist, .lib files, .sdc, derates, .spef gatelevel netlist, library .v, .sdf, test vectors, expected
output.
Basics of Static Timing analysis
- Much faster than timing-driven, gate-level simulation.
- Proper circuit functionality is not checked.
- Vector generation NOT required.

It is used to determine all the possible timing violations

including setup, hold, recovery removal and min_pulse_width
in a design for a specified clock, without applying test
vectors.

8
Timing paths
- Three main steps are followed by STA tools (ex. Pt):
1. Circuit is broken down into sets of timing paths.
2. Delay of each path is calculated.
3. Path delays are checked to see if timing constraints have been met.

A timing path is a point-to-point path in a design which can propagate data

from one flip-flop to another

9
Timing Path
Types
There are 4 types of paths in any
synchronous circuit
register-to- register-to-
input-to-register
register(reg2r output
(in2reg)
eg) (reg2out)

D Q D Q
DFF DFF

CLK CLK

Cloc
k
Input-to-
output
Combination
(in2out) al Logi
c

10
Timing paths
- A path is a route from a Startpoint to an Endpoint
• A startpoint can be:
1. clock pin of a FF,
2. An input port.
• An endpoint can be:
1. Input data pin of a FF
2. An output port.

Remember that STA is exhaustive, therefore:

- Many paths can be going to any one endpoint.
- Many paths can exist for each startpoint to endpoint combination.

11
Required
Time
Required time specifies the time point (interval) at which data is required to arrive at
end point (data is
required to be stable after arrival).
Time point after which data can become unstable (change) is called earliest required time
Time point after which data cannot become unstable (change) is called latest required time
The requirement is set by timing constraints like setup/hold, removal/recovery, etc.
cycle cycle
1 2

clock

Hold violation
will occur here
Setup
latest violation will
earliest
required required occur here
time time

12
Arrival Time
Arrival time defines the time interval during which a data signal will arrive at a path endpoint
(after arrival time
signal will be stable).
D ata is normally triggered by clock edge
Data arrival depend on circuit delay, which vary (depend on temperature, supply voltage, etc.)
Minimum delay, early arrival
Maximum delay, late arrival

CLOCK
earlies
tarrival
time

latest
arrival
Data mi time
Signal n
ma
x

13
Slack and Critical
Path
�
�

setu setu
p p
cloc cloc
k k

dat dat
a a

14
Early and Latest
Analysis
STA tool calculates the slack of each logic path, in order to find critical path.
Early and Latest analysis approaches:
Assumes circuits have minimum delay, compares arrival time to earliest required time (hold check)
Assumes circuits have maximum delay, compares arrival time to latest required time (setup check)

setu setu
p p
cloc cloc
k k

dat dat
a a

15
 Clocked Storage Elements
Transparent Latch, Level Sensitive
– data passes through when clock high, latched when
clock low

D-Type Register or Flip-Flop, Edge-Triggered

– data captured on rising edge of clock, held for rest
of cycle

1
4
Flip-Flops: Review of Internal Operation

The main cause for setup and hold time requirements is the
feedback mechanism of the internal FF latches.

Setup time: the time the input should be stable BEFORE the
active clock edge, needed by first latch to sample the input
and store it correctly. [always > 0]
FF propagation delay (T[clk-to-Q]): the time
Hold time: the time the input should be stable After the needed by the slave latch to propagate the sampled
active clock edge, needed by the first latch to make sure no value by master latch to its output, AFTER the active
new value is sampled while the sampled logic value is being clock edge.
held, avoiding race conditions. [can be >0, 0, or <0 !!]
Flip-Flops: Review of Internal Operation

18
Setup time

19
Hold Time

20
How FlipFlop works

21
Timing Verification of
Synchronous Designs
A D -FF is characterized by 3 main
parameters:
1. T[clk-to-q] – clock to output
2. T[setup] – setup time.
3. T[hold] – hold time
FF1
FF2
Q
F1 D
clk F1
Clk clk

0 2 4

22
T[clk-to-q]
indicates the amount of time needed for a change in the flip flop-
clock input (e.g.
rising edge) resulting in a permanent change at the flip-flop output
(Q).

23
T[setup]
• Setup time is the minimum amount of time the data input
should be held steady before the clock event, so that the data
is reliably sampled by the clock.

24
T[hold]
• Hold time is the minimum amount of time the data input should
be held steady after the clock event, so that the data is reliably
sampled by the clock.
• It’s not dependent on clock period!

25
The requirements of Setup and
Hold on timing paths

For T[clk-to-Q] + Tcomb + T[setup] ≤

Setup: Tclk + Tskew
For Hold: T[clk-to-Q] + Tcomb ≥ Thold
+ Tskew
26
Timing Constraints
There are two main problems that can arise in a digital circuit:
1) Max Delay: the data doesn’t have enough time to pass from one
register to the next
before the next clock edge.
2) Min Delay: the data path is so short that it passes through several
registers during the
same cycle.

The data has to stay stable at point B, for

The data has to arrive at point B,Tsetup Thold after
before the active clock edge. the active clock edge.
 Therefore, the new data to be sampled
2 delayed
has to beby [Tcq + Tprop] of at 27
1 least Thold!
Interactive Flip-Flop operation, timing
requirements

https://web.archive.org/web/20200701120033/http://onmy
phd.com/?p=flip.flop

28
What is
metastability?
 Whenever there are setup and hold time violations in any flip-flop, it enters a state
where its output is unpredictable: this state is known as metastable state (quasi
stable state);

 At the end of metastable state, the flip-flop settles down to either '1' or '0'.

 Whenever the input signal D does not meet the Tsetup and Thold of the given D
flip-flop, metastability occurs.

29
Exercise
For verifying chip proper operation; can we rely only on simulation or STA?

Where does optimization and analysis tools obtain a specific library FF characterstics
(tc2q/tsetup/thold)?

Should we seek or avoid positive skew?

30 30
Back to Timing Paths

Synopsys timing reports

format
 Static Timing Verification of FF2:
Setup FF1
FF2
Q
F1 U2 D
0ns 4ns
CLK
U3 F1
Clk CLK

FF1/clk 5.1ns
1.1ns

FF2/D

Setup

FF2/clk
1ns 5ns
PrimeTime Terminology
Data
FF1 Arrival
FF2
Q
F1 U2 D
CLK
U3 F1
Clk CLK

Data Required

Data
Slack is the difference
Arrival
between
Time
data arrival and data
FF1/clk required.
1.1ns 5.1ns
Data
FF2/D Required
Time
Setup

FF2/clk
1ns 5ns
 Four Sections in a Timing
Report
report_timing
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Header Path Group: Clk
Path Type: max

Point Incr Path

clock Clk (rise edge) 0.00 0.00

clock network delay (propagated) 1.10 * 1.10
Data FF1/CLK (fdef1a15) 0.00 1.10 r
FF1/Q (fdef1a15) 0.50 * 1.60 r
rrival
a U2/Y (buf1a27) 0.11 * 1.71 r
U3/Y (buf1a27) 0.11 * 1.82 r
FF2/D (fdef1a15) 0.05 * 1.87 r
data arrival time 1.87

clock Clk (rise edge) 4.00 4.00

Data clock network delay (propagated) 1.00 * 5.00
FF2/CLK (fdef1a15) 5.00 r
required library setup time -0.21 * 4.79
data required time 4.79

data required time 4.79

data arrival time -1.87
Slack
slack (MET) 2.92
The
Header
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Header Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: max
Capture clock

Report is for setup

FF1
FF2
Q
F1 U2 D
CLK
U3 F1
Clk CLK

35
Data Arrival
Section Calculated
latency
Point Incr Path

clock Clk (rise edge) 0.00 0.00

clock network delay (propagated) 1.10 * 1.10
FF1/CLK (fdef1a15) 0.00 1.10 r
Data FF1/Q (fdef1a15) 0.50 * 1.60 r
arrival U2/Y (buf1a27) 0.11 * 1.71 r
Library reference names
U3/Y (buf1a27) 0.11 * 1.82 r
FF2/D (fdef1a15) 0.05 * 1.87 r
data arrival time 1.87

.11ns
.11ns
.50ns .05ns
1.1ns Q
F1 r U2 D
r U3 r
r CLK r F1
0 2 4
FF1 CLK
Clk
FF2
Data Required
Section Point Incr Path

clock Clk (rise edge) 0.00 0.00

clock network delay (propagated) 1.10 * 1.10
FF1/CLK (fdef1a15) 0.00 1.10 r
FF1/Q (fdef1a15) 0.50 * 1.60 r
U2/Y (buf1a27) 0.11 * 1.71 r
U3/Y (buf1a27) 0.11 * 1.82 r
FF2/D (fdef1a15) 0.05 * 1.87 r
data arrival time 1.87

clock Clk (rise edge) 4.00 4.00

clock network delay (propagated) 1.00 * 5.00
Data FF2/CLK (fdef1a15) 5.00 r
required library setup time -0.21 * 4.79
data required time 4.79

FF1
FF2
Q
F1 U2 D 0.21ns
0 2 4 1.0ns CLK
U3 F1
r
Clk CLK
 Summary -
Slack
report_timing
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: max

Point Incr Path

clock Clk (rise edge) 0.00 0.00

clock network delay (propagated) 1.10 * 1.10
FF1/CLK (fdef1a15) 0.00 1.10 r
FF1/Q (fdef1a15) 0.50 * 1.60 r
U2/Y (buf1a27) 0.11 * 1.71 r
U3/Y (buf1a27) 0.11 * 1.82 r
FF2/D (fdef1a15) 0.05 * 1.87 r
data arrival time 1.87

clock Clk (rise edge) 4.00 4.00

clock network delay (propagated) 1.00 * 5.00
FF2/CLK (fdef1a15) 5.00 r
library setup time -0.21 * 4.79
data required time 4.79

data required time 4.79

Slack data arrival time -1.87

slack (MET) 2.92

Static Timing Verification of FF2:
Hold
FF1
FF2
Q
F1 U2 D
0ns 4ns CLK
U3 F1
Clk CLK

FF1/clk 5.1ns
1.1ns

FF2/D STABLE

Hold

FF2/clk
1ns 5ns

For H o ld: T[clk-to-Q ] + Tcom b ≥ Thold + Tskew

Which Edges are Used in a Timing
Report? FF1
FF2
Q
F1 U2 D
0ns 4ns U3 F1
CLK
Clk CLK

FF1/clk 5.1ns
1.1ns

FF2/D

Hold Setup

FF2/clk
1ns 5ns
 PrimeTime
Terminology FF1
Data Arrival

FF2
Q
F1 U2 D
0ns 4ns U3 F1
CLK
Clk CLK

Data Required

Data Arrival

FF1/clk 5.1ns
1.1ns
Slack is the difference
FF2/D between data arrival
and required.
Data Hold
Required
FF2/clk
1ns 5ns
Example Hold Timing
Report
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: min

Point Incr Path

clock Clk (rise edge) 0.00 0.00

clock network delay (propagated) 1.10 * 1.10
FF1/CLK (fdef1a15) 0.00 1.10 r
FF1/Q (fdef1a15) 0.40 * 1.50 f
U2/Y (buf1a27) 0.05 * 1.55 f
U3/Y (buf1a27) 0.05 * 1.60 f
FF2/D (fdef1a15) 0.01 * 1.61 f
data arrival time 1.61

clock Clk (rise edge) 0.00 0.00

clock network delay (propagated) 1.00 * 1.00
FF2/CLK (fdef1a15) 1.00 r
library hold time 0.10 * 1.10
data required time 1.10

data required time 1.10

data arrival time -1.61

slack (MET) 0.51

Exercis
e1. Identify all timing paths [assume i/p delay constraint =
0.3ns]
2. Calculate max. clock frequency

Setup requirement = 0.4 ns

for both FF’s

43
Exercise: Is there any setup or hold violation in this
circuit?

Assume i/p delay constraint

= 0.3ns
44
3- Design Constraints

45
Timing Constraints
• “Simple Question”:
• How does the STA tool know what the required clock
period is?
• Obvious Answer…
• We have to tell it!
• We have to define constraints for the design.
• This is usually done using the Synopsys Design Constraints
(SDC) syntax,
which is a superset of TCL.
• Three main categories of timing constraints:
• Clock definitions
• Modeling the world external to the chip 46
Design Objects [for all Synopsys
tools]
Design: A circuit description that performs some logical function.
The design may be stand-alone or may include other sub-designs.
Cell: It is the instantiated name of the sub-design in the design.
Reference: The original design to which the cell or instance refers.
For example, a leaf cell in the netlist must be referenced from the link library,
which contains the functional description of the cell. Similarly an
instantiated sub-design must be referenced in the design, which contains
functional description of the instantiated sub- design.

Port: These are the primary inputs, outputs or IO’s of the design.
Pin: It corresponds to the inputs, outputs or IO’s of the cells in the design.
(Note the difference between port and pin).
Net: These are the signal names, i.e., the wires that hook up the
design together by connecting ports to pins and/or pins to each
other.
Clock: The port or pin that is identified as a clock source.The identification
may be internal to the library or it may be done using dc_shell 47
commands.
 Design Objects [for all Synopsys
tools]
Por Cell Pi D esi
gn
t Net n
U1 U4
A U2
A. AIN BUS0 INV0 OUT1[1:0]
B Q0 INV D0 Q[1:0]
B.
C. C U3
BIN BUS1 INV1 D1
D INV
D. Q1
CLK
CIN CLK
Clock REGFILE
CLK CLK
DIN
RISC_CORE
E
N
The netlist
C defines 5 of the objects; you
O
define theD 6th:
E
create_clock –period 4 [get_ports CLK]
R
48
Stored as an attribute on the clock object.To see all attributes on the
Timing Constraints
Three main categories of timing
constraints:
1. Timing definitions
2. Optimization goals and timing
exceptions.
3. Modeling the world external to the
chip.

49
 Timing Constraints:
Categories
Timing Modeling outside world Optimization goals
and Timing
exceptions
create_clock set_driving_cell set_false_path
create_generated_clo set_load set_multicycle_path
ck set_max_delay set_input_delay
set_clock_uncertainty set_output_delay set_max_area
set_max_transition
set_max_capacitanc
e set_max_fanout

50
Clock …. create
Create_clock  The create_clock command creates a clock object in the current design.The command
defines the specified source_objects as clock sources in the current design. A pin or port can be a source
for a single clock.
EX:
# Create a master clock with name CLKP of period 10ns
# with 50% duty cycle at the CLKOUT pin of the PLL.

create_clock -name CLKP 10 [get_pins UPLL0/CLKOUT]

51
 Clock …. Generated
create_generated_clock :

 The create_generated_clock command creates a generated clock object in the current design.
 This command defines a list of objects as generated clock sources in the current design. You can specify a
pin or a port as a generated clock object.
 The command also specifies the clock source from which it is generated. The advantage of using this
command is that whenever the master clock changes, the generated clock changes automatically.

EX:
#The following example creates a frequency -divide_by 2 generated clock:

create_generated_clock -name CLKPDIV2 -source UPLL0/CLKOUT \

-divide_by 2 [get_pins UFF0/Q]

52
 set_clock_uncertainty and Setup Timing
Example:
create_clock -period 2 [get_ports CLK]
set_clock_uncertainty –setup 0.14 [get_clocks CLK]

D Q X D Q
FF1 FF2 FF2 setup check at:
2 - 0.14 - 0.08 =
1.78

FF1 Data Launch Edge

(No uncertainty!) / /
.14 .08

0 1 1.78 1.92 2
Max allowable delay
for block “X” Assume lib
setup = 0.08ns
53
Clock Specification for
Synthesis
Each clock in the design must be defined using the create_clock command.

Input delay constraint, and output delay constraint: define the length of the path OUTSIDE the block.

Example.
set_input_delay –max 0.8 –clock clk [remove_from_collection[all_inputs] [get_portsclk]]

set_output_delay –max 2.5 –clock clk [all_outputs]

54
Combinational
Designs
Sometimes the design is a combinational circuit
There is no clock to constraint timing

Circuit under
design

Combinatio
nal
Logic

55
Combinational Designs
(2)
Combinational circuit is put in the same clocked environment as the clocked one
An abstract clock called “Virtual clock” is defined for this environment
By setting correct clock period, input/output delays, the delay of the combinational logic can be
controlled

Combination Q
D
D Q al DFF
DFF
Logic CLK
CLK

Cloc
k
Delaymax= Tclk– Delayin – Delayout=3ns
Delayin=1ns
Delayout=7ns

56
set_min_delay set_max_delay
This command sets the minimum delay target for paths This command Specifies the desired maximum
in the current design. Minimum delay is considered as delay for paths in the current design.
an optimization constraint by the compile command.
This command specifies that the maximum path
If a path violates the requirement given in a length for any start point in from_list to any
set_min_delay command, compile adds delay to fix the endpoint in to_list must be less than delay_value.
violation.

EX: EX:
In the following example, the set_min_delay command The following example shows how to optimize
requires that any delay path that passes through the the design so any delay path to a port named Y
UI cell and ends at the Y port is greater than 12.5 time is less than 10 units.
units:

#set_min_delay 12.5 -through U1 -to Y #set_max_delay 10.0 -

to {Y}
57
Boundary Conditions
For modeling the world outside the block, we need to model:
1) The transitions on the input
2) A load capacitance on the output.

Example.
set_driving_cell –cell [get_lib_cells LIB/BUF2] -pin X [remove_from_collection [all_inputs]
[all_clocks] ]

set_input_transition 0.02 [remove_from_collection [all_inputs] [all_clocks] ]

set_load 0.12 [all_outputs]

58
 Exercise 0.3ns
0.3n
Setup
s
Time
TO_BE_SYNTHESIZED Requireme
nt
D Q M N D Q X D Q S T D Q
FF1 FF2 FF3 FF4
QB QB

Clk
Tclk= 2ns
 set_output_delay –max:
 Describes the maximum time requirement of the external logic on the output ports
Note: we should make sure that our design helps the assumed FF outside the block to
meet its setup requirements! By choosing the appropriate value for max_output_delay
If FF has TSETUP = 0.3ns and TT = 0.3ns:
What is the max output_delay?
 Constraining Input Paths:
Example 1
Spec: Latest Data Arrival Time at Port A, after Jane’s launching clock edge = 0.6ns

create_clock -period 2 [get_ports Clk]

set_input_delay -max 0.6 -clock Clk [get_ports A]

MY_DESIGN
JANE’s_DESIGN TSetup, FF2
0.2ns
Tmax
A
D Q M N D Q X D Q S
FF1 FF2 FF3
0.6ns
QB QB QB

Clk

What is the maximum delay Tmax for the input path N in MY_DESIGN?

60
Constraining Output Paths :
Example 1
Spec: Latest Data Arrival Time at Port B, before Joe’s capturing clock = 0.8ns

create_clock -period 2 [get_ports Clk]

set_output_delay -max 0.8 -clock Clk [get_ports B]

JOE’s_DESIGN
MY_DESIGN TT +
Tsetup
Tmax 0.7ns 0.1ns
B
N D Q X D Q S T D Q
FF2 FF3 FF4
QB QB QB
Clk

What is the maximum delay Tmax for the output path through S in MY_DESIGN?
 Multiple Inputs/Outputs - Same
Constraints A
MY_DESIGN
Out1
M
D Q S
B

C Out2
N D Q T
Clk

To constrain all inputs the same, except for the clock port:
set_input_delay –max 0.5 –clock Clk \
[remove_from_collection [all_inputs] [get_ports Clk]]

To constrain all outputs the same:

set_output_delay –max 1.1 –clock Clk [all_outputs]
Time Budgeting
Example timing_budget.tcl

# A generic Time Budgeting script file

# for MY_BLOCK, X_BLOCK and Y_BLOCK
create_clock -period 10 [get_ports CLK]

set_input_delay -max 6 -clock CLK [all_inputs]

remove_input_delay [get_ports CLK]
set_output_delay -max 6 -clock CLK [all_outputs]

X_BLOCK MY_BLOCK Y_BLOCK

X D Q N D X D Q
S Q S N D Q X
FF1 FF2 FF3 FF4
10 4 4 10 4 4 10
False Paths

Timing paths that are logically impossible!

Even if they violate a timing requirement according to STA, the data would
never propagate
through this path in actual circuit operation.. No need to meet any timing
constraint 

Therefore, we need to specify it to STA tools to avoid analyzing/reporting it.

Example.
set_false_path – through [get_pins Mux1/In0] – through [get_pins
False path
examples
set_false_path -from [get_clocks SCAN_CLK]
-to [get_clocks CORE_CLK]
set_false_path -to [get_ports
# Any path starting from the SCAN_CLK domain to TEST_REG*]
the # All paths that end in port named TEST_REG* are
# CORE_CLK domain is a false path. false paths.

set_false_path -through [get_pins UMUX0/S]

# Any path going through this pin is
false. set_false_path -through UINV/Z -through
UAND0/Z

set_false_path -through [get_pins # Any path that goes through both of these
SAD_CORE/RSTN]] pins in this order is false.

# The false path specifications can be also

specified to, through, or from a module pin
instance.
 Exercise

-Do we need to specify false paths to synthesis and

physical synthesis as well?

-What are the consequences of not accurately

specifying false paths? [list two of them]

6 66
2
Multi-cycle
Paths
There are data paths that require more than one clock period for execution.

2 clock period delay

6 67
0
 Multi_cycle Paths
In some cases, the combinational data path between two flip-flops can take more
than one clock cycle to propagate through the logic.
In such cases, the combinational path is declared as a multi cycle path.
Even though the data is being captured by the capture flip-flop on every clock edge,
we direct STA that the relevant capture edge occurs after the specified number of
clock
cycles.
Since the data path can take up to three clock cycles, a setup multi cycle check of three
cycles should be specified.

68
 Multi_cycle
Paths
The multi cycle setup constraints specified to achieve this are given below.
create_clock -name CLKM -period 10 [get_portCLKM]
set_multicycle_path 3 -setup \
-from [get_pins UFF0/Q] \
-to [get_pins UFF1/D]
The setup multi cycle constraint specifies that the path from UFF0/CK to UFF1/D
can take up to three clock cycles to complete for a setup check.
This implies that the design utilizes the required data from UFF1/Q only every third cycle instead
of every cycle.

set_multicycle_path 2 –hold \
-from [get_pins UFF0/Q] \
-to [get_pins UFF1/D]

69 69
 A three cycle multipath

70
What happens when we
cross-domain?

71
 Case
analysis
A common case for designs is that some value should be assumed constant.
-For example; if the constant sets a multiplexer selector

-To propagate this constant through the design and disable irrelevant timing arcs, a
set_case_analysis constraint is used

-Example.
set_case_analysis 0 [get_ports testMode]
 Logical Design
Rules
set_max_transition 0.15
Sets the maximum transition time for all nodes of the design.

set_max_capacitance 0.08
Sets the maximum capacitance of a net for all nodes of the design.

set_max_fanout 10
Set the maximum number of load cells a pin can be connected to.
 Exercise
-What are the pros and cons of:
A. Setting a relatively high value for max. transition.
B. Setting a very tight value for max. transition.

-What are the pros and cons of setting a relatively low value for
max. fanout?
Exerci
se
4ns For all
Buf2 1ns 2ns 3ns 1ns 1ns 2ns
-FFs:
Tcq=0.04ns
- Tsetup=0.05
10 fF
ns
- Thold=0.03
4ns 2ns ns
2ns 2ns

PLL jitter=
0.1ns
/2 /2

Write and SDC file for each of BLOCK A and BLOCK B

- For each input port; specify a suitable I/P delay constraint and boundary conditions.
- For each output port; specify a suitable O/P delay constraint and boundary conditions.
- For each clock and generated clock, specify it properly for each block.
- Clarify that CK1 and CK2 don’t have inter-clk paths.