SYSTEM DESIGN WITH

FPGA U18ECE004
2

CYCLE BASED DRIVEN

SIMULATION
GROUP – 6:

1) JENESHA P – 21BEC054
2) JENIFERRAJ J – 21BEC055
3) KAAVYA K – 21BEC056
4) KALAISELVAN P – 21BEC057
5) KARTHI S V – 21BEC059
What is Cycle-Based
Simulation?
 A simulation technique where the design’s
behavior is evaluated on a cycle-by-cycle
basis.
 Each clock cycle’s state is computed,
making it more deterministic and
predictable.
Definition:
 Cycle-based simulation simulates digital circuits where the
simulation progresses in discrete time steps, often
corresponding to clock cycles.

Key Characteristics:
 Synchronous operation: Relies on a clock signal to define
the timing of events.
 Discrete time steps: Simulation advances in fixed intervals.
 Boundary node evaluation: Only the values at the
boundaries of combinational logic blocks are evaluated.
Why Cycle-Based Simulation for FPGA?
Accuracy:
o Provides precise timing accuracy compared to event-driven
simulation.
Deterministic Behavior:
o Simulates circuits by evaluating the state of the system at each clock
cycle.
Performance:
o Faster than event-driven simulation as it doesn’t have to track
multiple events occurring in between clock cycles.
Simplicity:
o Easier to handle for synchronous designs, which are common in
FPGA development.
Cycle-Based Simulation Algorithm
i. Initialize: Set the initial values of all state elements and
boundary nodes.
ii. Evaluate Boundary Nodes: Calculate the new values of
boundary nodes based on their inputs and the current
state of the circuit.
iii. Update State Elements: Store the new values of
boundary nodes in the corresponding state elements.
iv. Repeat: Go back to step 2 and repeat the process until
the desired number of clock cycles has been simulated.
FPGA Design Workflow with Cycle-Based
Simulation
i. Design Specification : Define system behaviour.
ii. HDL Coding: Write the design using Verilog or VHDL.
iii. Cycle-Based Simulation: Simulate the design cycle-by-cycle.
iv. Synthesis: Convert the HDL code to logic gates.
v. Place and Route: Assign logic blocks and routes on the FPGA.
vi. Timing Analysis: Ensure the design meets timing constraints.
Cycle-Based Simulation Tools for FPGA
 ModelSim:
A tool for cycle-based simulation of VHDL/Verilog
designs.
 Vivado Simulator:
Xilinx supports cycle-based simulation.
 Questa Advanced Simulator:
Used for both event-driven and cycle-based
simulations.
Benefits of Cycle-Based Simulation in FPGA
 Higher Speed:
o Offers faster simulation time for large, synchronous
designs compared to event-driven simulation.
 Timing Precision:
o Accurate representation of clocked circuit behavior
in each clock cycle.
 Easier Debugging:
o Easier to debug synchronous systems as behavior is
evaluated at each clock edge.
Challenges with Cycle-Based Simulation

 Limited for Asynchronous Designs:

o Not ideal for systems that depend on asynchronous
events.
 Simplified View of Timing:
o Some low-level timing issues may not be easily
captured in cycle-based simulation.
 Resource Intensive for Large Designs:
o May require significant computational resources for
very complex designs.
 Event-Driven vs Cycle-Based Simulation
Feature Cycle-Based Simulation Event-Driven Simulation

Timing Model Synchronous Asynchronous

Scheduling Based on clock cycles Based on events

Evaluation Boundary nodes All nodes

Speed Faster Slower

Both synchronous and asynchronous

Applicability Synchronous circuits
circuits

Accuracy Less accurate for timing anomalies More accurate for timing anomalies

Debugging Easier for synchronous designs More complex for timing-related issues

May require more resources for complex

Resource Usage More efficient for large designs
simulations
Advantages of Cycle-Based Simulation
 Speed:
Typically faster than event-driven simulation due to its simpler
scheduling mechanism.
 Simplicity:
Easier to implement and understand due to its straightforward
approach.
 Efficiency:
Can be optimized for synchronous circuits, leading to reduced
simulation time.
Disadvantages of Cycle-Based Simulation

 Limited Applicability:
Less suitable for asynchronous circuits or circuits with
complex timing relationships.
 Reduced Accuracy:
May not accurately capture certain timing anomalies or
glitches.
 Difficulty in Debugging:
It can be challenging to debug timing-related issues.
Applications of Cycle-Based Simulation
 Digital IC Verification:
Verifying the functional correctness of digital integrated circuits.
 Hardware/Software Co-Simulation:
Simulating the interaction between hardware and software
components.
 Performance Analysis:
Evaluating the performance of digital systems, such as latency and
throughput.
 Fault Simulation:
Identifying potential faults in digital circuits.
Implementation Techniques
 HDL-Based Simulation:
Using hardware description languages (HDLs) like Verilog
or VHDL to describe the circuit and simulate it.
 Specialized Simulators:
Employing dedicated simulators optimized for cycle-
based simulation.
 Hardware Emulators:
Using hardware emulators to provide faster and more
accurate simulations.
Implementation Considerations
 Hardware Description Languages (HDLs):
Cycle-based simulation can be implemented using HDLs like Verilog
and VHDL.
 Simulation Tools:
Many commercial simulation tools support cycle-based simulation,
including Synopsys VCS, Cadence Incisive, and Mentor QuestaSim.
 Timing Analysis:
While cycle-based simulation can be used for functional
verification, it is not suitable for detailed timing analysis. For timing
verification, event-driven simulation or static timing analysis should be
used.
Conclusion
 Cycle-based simulation is a valuable technique for
simulating synchronous digital circuits.
 Its speed, simplicity, and efficiency make it suitable
for many applications.
 However, its limitations in handling asynchronous
circuits and timing anomalies should be considered
when choosing
the appropriate simulation method.
THANK YOU !