Unit-3

Basic Processing Unit

 Introduction
• The organization of processors has evolved over the
years, driven by developments in technology and the
need to provide high performance.

• A common strategy in the development of high-

performance processors is to make various functional
units operate in parallel as much as possible
• High-performance processors have a pipelined
organization where the execution of one instruction is
started before the execution of the preceding
instruction is completed.
• In another approach, known as superscalar op-
eration, several instructions are fetched and executed
at the same time.
 Introduction
• The organization of processors has evolved over the years, driven
by developments in technology and the need to provide high
performance.

• A common strategy in the development of high-performance

processors is to make various functional units operate in parallel
as much as possible
• High-performance processors have a pipelined organization
where the execution of one instruction is started before the
execution of the preceding instruction is completed.
• In another approach, known as superscalar operation, several
instructions are fetched and executed at the same time.
 7.1 SOME FUNDAMENTAL CONCEPTS
• To execute a program, the processor fetches one
instruction at a time and performs the operations
specified.
• Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
• The processor keeps track of the address of the memory
location containing the next instruction to be fetched
using the program counter, PC.
• After fetching an instruction, the contents of the PC are
updated to point to the next instruction in the sequence.
 SOME FUNDAMENTAL CONCEPTS
• To execute an instruction, the processor has to perform the
following three steps:

1. Fetch the contents of the memory location pointed to by the PC.

The contents of this location are interpreted as an instruction to
be executed. Hence, they are loaded into the IR.
Symbolically, this can be written as
IR < [[PC]]

2. Assuming that the memory is byte addressable, increment the

contents of the PC by4, that is,
PC < [PC] + 4

3. Carry out the actions specified by the instruction in the IR.

 SOME FUNDAMENTAL CONCEPTS
• If Instruction occupies more than one word,
steps 1 and 2 must be repeated as many times
as necessary to fetch the complete instruction.
• These two steps are usually referred to as the
fetch phase; step 3 constitutes the execution
phase.
 Processor Organization
• This bus is internal to the processor and should not be
confused with the external bus that connects the
processor to the memory and 1/0 devices.
• The data and address lines of the external memory bus
are shown in Figure 7.1 connected to the internal
processor bus via the memory data register, MDR, and the
memory address register, MAR, respectively.
• Register MDR has two inputs and two outputs. Data may
be loaded into MDR either from the memory bus or from
the internal processor bus. The data stored in MDR may
be placed on either bus.
 Processor Organization
• The input of MAR is connected to the internal bus,
and its output is connected to the external bus.
• The control lines of the memory bus are connected
to the instruction decoder and control logic block.
• This unit is responsible for issuing the signals that
control the operation of all the units inside the
processor and for interacting with the memory bus.
 Processor Organization
• The number and use of the processor registers
RO through R(n - 1) vary considerably from
one processor to another.
• Registers may be provided for general-
purpose use by the programmer.
• Some may be dedicated as special-purpose
registers, such as index registers or stack
pointers. Three registers, Y, Z, and TEMP in
Figure 7.1, have not been mentioned before.
 Processor Organization
• These registers are transparent to the
programmer, that is, the programmer need
not be concerned with them because they are
never referenced explicitly by any instruction.
• They are used by the processor for temporary
storage during execution of some instructions.
These registers are never used for storing data
generated by one instruction for later use by
another instruction.
 Processor Organization
• As instruction execution progresses, data are
transferred from one register to an-other,
often passing through the ALU to perform
some arithmetic or logic operation.
• The instruction decoder and control logic unit
is responsible for implementing the actions
specified by the instruction loaded in the IR
register.
 Processor Organization
• The multiplexer MUX selects either the output
of register Y or a constant value 4 to be
provided as input A of the ALU.
• The constant 4 is used to increment the
contents of the program counter.
• We will refer to the two possible values of the
MUX control input Select as Select and Select
Y for selecting the constant 4 or register Y,
respectively.
 Processor Organization
• The decoder generates the control signals
needed to select the registers involved and
direct the transfer of data.
 Executing an Instruction
• Transfer a word of data from one processor
register to another or to the ALU.
• Perform an arithmetic or a logic operation and
store the result in a processor register.
• Fetch the contents of a given memory location
and load them into a processor register.
• Store a word of data from a processor register
into a given memory location
 SOME FUNDAMENTAL CONCEPTS
• A branch instruction may load a different
value into the PC.
• Another key register in the processor is the
instruction register, IR.
• Suppose that each instruction comprises 4
bytes, and that it is stored in one memory
word.
 Overview
• Instruction Set Processor (ISP)
• Central Processing Unit (CPU) 
A typical computing task consists of a
series of steps specified by a sequence of
machine instructions that constitute a program.
• An instruction is executed by carrying out a
sequence of more rudimentary operations
 Fetching a Word from Memory 
• Address into MAR;issue Read operation; data into MDR.
 Fetching a Word from Memory
• The response time of each memory access varies (cache
miss, memory-mapped I/O,…). 
• To accommodate this, the processor waits until it receives an
indication that the requested operation has been completed
(Memory-Function-Completed, MFC).
• Move (R1), R2
 MAR ← [R1]
 Start a Read operation on the memory bus
 Wait for the MFC response from the memory
 Load MDR from the memory bus
 R2 ← [MDR]
Timing
 Execution of a Complete Instruction
 Add (R3), R1
 Fetch the instruction
 Fetch the first operand (the contents of the
memory location pointed to by R3)
 Perform the addition
 Load the result into R1
Execution of a Complete Instruction
 Execution of Branch Instructions
• A branch instruction replaces the contents of
PC with the branch target address, which is
usually obtained by adding an offset X given in
the branch instruction.

• The offset X is usually the difference between

the branch target address and the address
immediately following the branch instruction.
• Conditional branch
Execution of Branch Instructions
Multiple-Bus Organization
 Multiple-Bus Organization
Add R4, R5, R6
 Hardwired Control
• To execute instructions, the processor must
have some means of generating the control
signals needed in the proper sequence.
• Two categories: hardwired control and
microprogrammed control
• Hardwired system can operate at high speed;
but with little flexibility.
Control Unit Organization
Detailed Block Description
Generating Zin
Generating End
A Complete Processor
 Microprogrammed Control
• Control signals are generated by a program similar to machine
language programs.
• Control Word (CW); microroutine; microinstruction
Overview
Overview
Basic organization of a microprogrammed control unit.
Control store
Overview

Organization of the
control unit to allow
conditional branching
in the microprogram.
 Microinstructions
• A straightforward way to structure
microinstructions is to assign one bit position
to each control signal.
• However, this is very inefficient.
• The length can be reduced: most signals are
not needed simultaneously, and many signals
are mutually exclusive.
• All mutually exclusive signals are placed in the
same group in binary coding.
 Overview
• processing unit, which executes machine
instructions and coordinates the activities of other
units.
• This unit is often called the Instruction Set
Processor (ISP), or simply the processor.
• We examine its internal structure and how it
performs the tasks of fetching, decoding, and
executing instructions of a program.
• The processing unit used to be called the central
processing unit (CPU).
 Some Fundamental Concepts
• Fundamental Concepts
• Processor fetches one instruction at a time and
perform the operation specified.
• Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
• Processor keeps track of the address of the memory
location containing the next instruction to be
fetched using Program Counter (PC).
• Instruction Register (IR)
Hardware for Multiplication
Hardware implementation of Unsigned
Binary Numbers
Multiplying Signed Numbers
Booth’s Algorithm for Two’s Complement
Multiplication
Example for Booth’s Algorithm
Booth’s Algorithm
Binary Division for Unsigned Numbers
Consider the following: Dividend = 15 (place in Q) and Divisor = 8 (place in M)
Count n = 4
Hardware for Division
Non Restoring Method
Example Non Restoring Method
Non Restoring Binary Division