Design of Analog Integrated

Circuit
1

V O T UA N M I N H
Faculty of Electronics and Telecommunication Engineering
University of Science and Technology - The University of
Danang
 Thông tin chung
2

Giảng viên: Võ Tuấn Minh

 Email: [email protected]

Giáo trình
 Slides bài giảng
Tham khảo
 Behzad Razavi, Design of Analog CMOS Integrated

Circuits, McGraw-Hill
 Behzad Razavi, Fundamentals of Microelectronics, Wiley

Phân bố điểm
 Điểm danh + Bài tập: 30 %
 Giữa kì: 20%, tự luận
 Cuối kì: 50 %, tự luận

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 Chủ đề
3

Giới thiệu Thiết kế vi mạch & Đặc tính của

MOSFET
Mạch khuếch đại đơn
Mạch khuếch đại vi sai
Mạch gương dòng
Bộ chuyển đổi tương tự/số
Vòng khóa pha

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 Introduction to VLSI
Design
4

INTRODUCTION
A N A L O G V S. D I G I TA L
SUMMARY

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 Analog Signals
5

Analog signals
 Directly measurable quantities in terms of some

other quantity
 Continuous over time and space => “analogous” to

the physical signal it represents

Examples
Thermometer – mercury height rises as
temperature rises
Stereo – Volume increases as you turn the
knob
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 Digital Signals
6

Digital Signals – have only two states

 For digital computers, we refer to binary states, 0

and 1
 Sampled at discrete points in time and discrete

values (amplitude) => signal is quantized, so it is

an approximation

Examples
Light switch can be either on or off
Door to a room is either open or closed

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 Analog and Digital Signal
7

http://www.rpi.edu/dept/phys/ScIT/InformationTransfer/sigtransfer/images/analogdigital.gif

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 Why Digital?
8

Lower Power Consumption

Memory Function
Easy Design
 Automation, Standard Cell Libraries

Easy Post-Process
More Robust
More Room for Error
Flexible Implementation
Process as much as possible digitally!

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 Why Analog?
9

Physical Signals in Nature

 Sound, Video, Temperature, Distance…
Super High Frequency Transmitter
 Microwave, 60GHz, 77GHz…
Power Supply, Power Storage
Circuit Protection
 ESD (ElectroStatic Discharge)
 EMC (ElectroMagnetic Capability)
Analog circuit is indispensable piece!
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 Must-have Knowledge
10

 Small signal analysis

 Current references & voltage references
 Single stage & multistage differential amplifiers
 Op-amps & OTAs
 Frequency response of amplifiers
 Stability analysis of amplifiers
 Noise analysis
 Some device physics knowledge
 Knowledge of spice simulator tool & techniques to perform
analog and mixed signal circuit simulations
 “Art of analog layout design“: 50% of work. Learn how to do
systematic layout, symmetry requirements, common centroid
& inter-digitating techniques, off-set cancellation, noise
prevention & floor planning of your design.
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 Analog/Digital Design
11

Trend in IC Design now: 50% – 90% of

Digital and 50% - 10% of Analog
Scaling in CMOS good for Digital but not
for Analog
Mixed-signal design is very important now
because Analog parts do not stand alone
anymore
Software defined RF
Programmable Analog

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 Some VLSI Manufacturers
12

Fabrication Companies
 Integrated Device Manufacturers (IDM)
 Intel, Fujitsu, Samsung, Toshiba…
 Foundry, only manufacture
 TSMC, MediaTek…

Fabless Companies
 Design and sale of hardware devices and semiconductor

chips while outsourcing the fabrication of the devices to a

specialized manufacturer called a semiconductor foundry
 Qualcomm, Texas Instrument, AMD, Nvidia, Marvell, Apple…

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 CMOS Basics
13

PN JUNCTION
DEVICE STRUCTURE
P H Y S I C A L O P E R AT I O N
C U R R E N T-V O LT A G E C H A R A C T E R I S T I C S
THE BODY EFFECT AND OTHER TOPICS

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 Silicon Lattice
14

Transistors are built on a silicon substrate

Silicon is a Group IV material
Forms crystal lattice with bonds to four
neighbors
Si Si Si

Si Si Si

Si Si Si
 Dopants
15

Silicon is a semiconductor
Pure silicon has no free carriers and conducts
poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-
type) Si Si
-
Si Si Si
+
Si

+ -
Si As Si Si B Si

Si Si Si Si Si Si
 Tiếp giáp pn ở điều kiện cân bằng
nhiệt
16
Thiểu E
Nhiệt số - +
p −
-
- +
+ J n ,diff n
- +
− - +
-
- +
+
J p ,diff
J p ,drift -
- +
+
- +
J n ,drift -
-
+
+
- +

Vùng nghèo
Dòng khuếch tán nhỏ: chỉ ít hạt mang điện đủ năng
lượng
Dòng trôi nhỏ: hạt mang điện thiểu số (minority) rất
ít và xa
Dòng trôi độc lập với lớp ngăn!
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Dòng khuếch tán là hàm phụ thuộc mạnh (lũy
 Reverse Bias
17

Reverse Bias causes an increases barrier to

diffusion
Diffusion current is reduced exponentially
- +
p -
- +
+ n
- +
- +
- +
- + +
−

Drift current does not change

Net result: Small reverse current
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 Forward Bias
18

Forward bias causes an exponential increase

in the number of carriers with sufficient
energy to penetrate barrier
Diffusion current increases exponentially
- +
p -
- +
+ n
+ - +
- +
− - +
- +

Drift current does not change

Net result: Large forward current

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 CMOS Basics
19

PN JUNCTION
DEVICE STRUCTURE
P H Y S I C A L O P E R AT I O N
C U R R E N T-V O LT A G E C H A R A C T E R I S T I C S
SECOND ORDER EFFECTS
SMALL-SIGNAL MODEL

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 Device Structure
20

 Four-terminal device: gate (G), source (S), drain (D) and body
(B)
 The device size (channel region) is specified by width (W) and
length (L)
 Two kinds of MOSFETs: n-channel (NMOS) and p-channel
(PMOS)
 Source and drain terminals are specified by the operation V.T.M
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 Device Structure
21

 Charge carriers are electrons in NMOS devices,

and holes in PMOS devices
 Electrons have a higher mobility than holes. So,
NMOS devices are faster than PMOS devices
 Actual length of the channel (Leff) is less than the
length of gate (Ldrawn)
 Leff = Ldrawn - 2LD
 LD due to side diffusion
 Poly-silicon used instead
of Metal for fabrication
reasons
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 Device Structure
22

 CMOS technology employs both PMOS and NMOS

 n-wells allow both NMOS and PMOS devices to reside
on the same piece of die

 B of NMOS is connected to the most (-) voltage, and B

of PMOS is connected to the most (+) voltage
 To prevent effect of Schottky diode, use p+ and n+ for B

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 Symbols
23

 Symbols in (b) are the most widely used in analog

circuits
 Symbols in (c) are used in digital circuits

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 CMOS Basics
24

PN JUNCTION
DEVICE STRUCTURE
P H Y S I C A L O P E R AT I O N
C U R R E N T-V O LT A G E C H A R A C T E R I S T I C S
SECOND ORDER EFFECTS
SMALL-SIGNAL MODEL

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 Operation with Zero Gate Voltage
25

 The MOS structure form a

parallel plate-plate capacitor
with gate oxide layer in the
middle

 Two pn junctions (S/B & D/B) are connected as

back-to-back diodes
 The source and drain terminals are isolated by two
depletion regions without conducting current

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 Creating a Channel for Current Flow
26

 Positive charges accumulate in gate as a positive

voltage applies to gate electrode
 The electric field forms a depletion region by
pushing holes in p-type substrate away from the
surface
 Electrons start to accumulate on the substrate
surface as gate voltage exceeds a threshold
voltage VTH
 The induced n forms a channel region thus for
current flow from drain to source
 The channel is created by inverting the substrate
surface from p-type to n-type -> inversion layer

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2020 field controls the amount of charge in the V.T.M
 Applying a Small Drain Voltage
27

 Free electrons travel from source to drain through

the induced n-channel due to a small VDS

 The resulting current

ID flows from drain to
source (opposite to the
direction of the flow of
negative charge)

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 Applying a Small Drain Voltage
28

 The current is proportional to the number of

carriers in the induced channel
 The channel is controlled by the effective voltage
or overdrive voltage: Vov = VGS – VTH
 The electron charge in the channel due to
the overdrive voltage: |Q| = CoxWLVov
 Gate oxide capacitance Cox is defined
as capacitance per unit area
 MOSFET can be approximated as a linear resistor
in this region

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 Operation as Increasing Drain Voltage
29

 As VDS increases, the voltage along the channel

increases from 0 to VDS , and the voltage between the
gate and the points along the channel decreases from
VGS at the source end to (VGS – VDS) at the drain end
 Since the inversion layer depends on the voltage
difference across the MOS structure,
increasing VDS will result in a
tapered channel
 The resistance increases due
to tapered channel and the
ID /VDS curve does not
continue as a straight line

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 Operation as Increasing Drain Voltage
30

 At the point VDS,sat = VGS – VTH, the channel is

pinched off at the drain side
 Increasing VDS beyond this value has little effect on
the channel shape and ID saturates at this value

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 Enhancement/Depletion MOSFET
31

 If VGS > VTH then the channel is induced:

enhancement-type MOSFET
 If VGS > VTH then the channel is cut: depletion-
type MOSFET

https://www.google.com/url?
sa=i&source=images&cd=&cad=rja&uact=8&ved=2ahUKEwigxYWntfDmAhXSAYgKHd6LAhMQjhx6BAgBEAI&url=https%3A
%2F%2Ftogo.wpart.co%2Fmosfet-symbol%2F&psig=AOvVaw1yLZ1YF72aGNvOHLOETNJP&ust=1578449578618119
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 CMOS Basics
32

PN JUNCTION
DEVICE STRUCTURE
P H Y S I C A L O P E R AT I O N
C U R R E N T-V O LT A G E C H A R A C T E R I S T I C S
SECOND ORDER EFFECTS
SMALL-SIGNAL MODEL

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 Derivation of I/V Relationship
33

 The drain current ID is calculated by

 QD(x): mobile charge density per meter

v(x): velocity of the charge
E(x)


S D
 We have,

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 Derivation of I/V Relationship
34

Process transconductance parameter (μA/V2):

k’n = μnCox
Aspect ratio: W/L
Transconductance parameter (μA/V2): kn=
μnCox(W/L)

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 NMOS I/V Characteristics
35

The current-voltage characteristics

 Cut-off region: (V
GS ≤ VTH)

 Triode region: (VGS > VTH and 0 < VDS < VGS – VTH)

 Saturation: (VGS > VTH and VDS ≥ VDS,sat = VGS – VTH)

: square-law

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 NMOS I/V Characteristics
36

VDS << 2(VGS – VTH): linear region

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 Example
37

For the following circuit assume that

When is the device on?

What is the region of operation if the device

is on?

Sketch the on-resistance Ron of transistor M1

as a function of VG
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 Transconductance
38

The drain current of the MOSFET in

saturation region is ideally a function of
gate-overdrive voltage (effective voltage). In
reality, it is also a function of VDS
It makes sense to define a figure of merit
that indicates how well the device converts
the voltage to current
Which current are we talking about?
What voltage is in the designer’s control?
What is this figure of merit?
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 Transconductance
39

 Example: Plot the transconductance of the

following circuit as a function of VDS

 Transconductance in triode

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 Transconductance
40

 Transconductance in saturation:

 Moral: Transconductance drops if the device enters

the triode region

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 Transconductance
41

 Transconductance in saturation is also expressed

as:

W/L: hằng Vov: hằng ID: hằng

gm  Vov gm  W/L gm 
gm  gm  ID gm  1/Vov
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 CMOS Basics
42

PN JUNCTION
DEVICE STRUCTURE
P H Y S I C A L O P E R AT I O N
C U R R E N T-V O LT A G E C H A R A C T E R I S T I C S
SECOND ORDER EFFECTS
SMALL-SIGNAL MODEL

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 Channel Length Modulation
43

 The channel pinch-off point moves

slightly away from D as VDS > VDS,sat
 The effective channel length (Leff)

reduces with VDS

 The length accounted for conductance
in the channel is replaced by Leff

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 Channel Length Modulation

 assume that , or
44

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 Channel Length Modulation
45

 Example: Given all other parameters constant,

plot ID/VDS characteristic of an NMOS for L = L1
and L = 2L1
 Triode Region:

 Saturation Region:

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 Channel Length Modulation
46

 Changing the length of the device from L1 to 2L1

will flatten the ID/VDS curves (slope will be divided
by two in triode and by four in saturation)
 Increasing L will make a transistor a better current
source, while degrading its current capability
 Increasing W will improve the current capability

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 Finite Output Resistance
47

 VA (Early voltage) = V’AL; V’A: process-technology dependent

with a typical value from 5 ~ 50 V/µm
 Due to the dependence of ID on VDS, MOS FET shows finite
output resistance in saturation region

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 Body Effect
48

The BS and BD junction should be reverse

biased for the device to function properly
Normally, the body of a n-channel MOSFET is
connected to the most negative voltage
The depletion region widens in BS and BD
junctions and under the channel as VSB
increases
Body effect: VTH increases due to the excess
charge in the depletion region under the
channel
The body effect can cause considerable
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degradation in circuit performance
 Body Effect
49

 Threshold voltage:

where, and

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 Body Effect
50

Example: Consider the circuit below (assume

the transistor is in the active region). Plot the
difference of (Vin – Vout) with and without body
effect when Vout increases

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 Body Effect
51

 If body effect is ignored, VTH will be constant, I1 will

only depend on VGS1 = Vin – Vout. Since I1 is constant,
Vin – Vout remains constant
 In general, I1 depends on VGS1 – VTH = Vin – Vout – VTH
(with body effect, VTH is not constant). Since I1 is
constant
 Vin – Vout – VTH = C = Const. => Vin – Vout = VTH + C
 As Vout increases, VSB1 increases, VTH increases and
Vin - Vout increases

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 Body Effect
52

Example: For the following circuit sketch the

drain current of transistor M1 when VX varies
from -∞ to 0. Assume VTH0 = 0.3V, γ=0.4V1/2,
and 2ff = 0.7V.

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 CMOS Basics
53

PN JUNCTION
DEVICE STRUCTURE
P H Y S I C A L O P E R AT I O N
C U R R E N T-V O LT A G E C H A R A C T E R I S T I C S
SECOND ORDER EFFECTS
SMALL-SIGNAL MODEL

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 Device Capacitances
54

 The capacitances associated with the devices are

important when studying the AC behavior
 There are 6 Capacitances in total
 CDS = 0

 These capacitances will depend on the region of

operation (Bias values)
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 Device Capacitances
55

 The following will be used to calculate the

capacitances between terminals:
 Oxide Capacitance:
 Depletion Capacitance:
 Overlap Capacitance:
 Junction Capacitance:

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 Device Capacitances
56

In Cut-off
 C : is equal to
GS

 CGD: is equal to
 CGB: is equal to C1 in series with C2
 CSB: is equal to
 CDB: is equal to

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 Device Capacitances
57

In Triode:
 The channel isolates G from the substrate. Moreover,

change of VG draws equal amounts of charge from S

and D. Thus, C1 is equally divided between CGS and
CGD, and, C2 is equally divided between CSB and CDB.
 ,

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 Device Capacitances
58

In Saturation:
 Equivalent capacitance between S and G is

approximately (2/3)C1. Equivalent capacitance

between S and B is approximately (2/3)C2.
 ,

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 Device Capacitances
59

Cut-off Triode Saturation

CGB C1 nt C2 0 0
CDB C6 C6 + C6 + 2C2/3 Symmetrical
C2/2 structure
CSB C5 C5 + C5
C2/2
CGS C3 C3 + C3 + 2C1/3
C1/2
CGD C4 C4 + C4
C1/2

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 Small-Signal Models
60

 Small-signal model is an approximation of the

large-signal model around the operation point
 In analog, most transistors are biased in saturation
region
 In general, ID is a function of VGS, VDS and VBS

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 Small-Signal Models
61
Body
 Small-Signal Model: Effect

Channel Length
 Terms gmvGS and gmbvModulation
BS have the same polarity
,

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 Small-Signal Models
62

 Complete small signal model makes the intuitive

(qualitative) analysis of even a few-transistor circuit
difficult!
 Typically, CAD tools are used for accurate circuit
analysis
 For intuitive analysis, try to find the simplest model that
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can represent the role of each transistor with
 PMOS Small-Signal Model
63

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 Summary
64

Static power dissipation in CMOS is almost zero

Three operation regions in CMOS
 Cut-off region (VGS ≤ VTH):
 Triode region (VGS > VTH and VDS < VGS – VTH):

 Saturation (VGS > VTH and VDS ≥ VGS – V ):

TH

Pay attention much to second effects in short-

channel technology

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